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drm/exynos: clean up register definions for fimd and decon 

This patch removes suffixes from I80 relevant register definitions,
which are misleading.

This is based on top of below patch set,
     http://www.spinics.net/lists/dri-devel/msg104057.html

Signed-off-by: Inki Dae <inki.dae@samsung.com>
This commit is contained in:
Inki Dae 2016-04-12 09:59:11 +09:00 committed by Inki Dae
parent 9ac26de835
commit b5bf0f1ea3
3 changed files with 15 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
View File

@ -121,7 +121,7 @@ static void decon_setup_trigger(struct decon_context *ctx)
? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
: TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
TRIGCON_HWTRIGMASK | TRIGCON_HWTRIGEN;
writel(val, ctx->addr + DECON_TRIGCON);
}

23
drivers/gpu/drm/exynos/exynos_drm_fimd.c
View File

@ -68,15 +68,15 @@
/* color key value register for hardware window 1 ~ 4. */
#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
/* I80 / RGB trigger control register */
/* I80 trigger control register */
#define TRIGCON 0x1A4
#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
#define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
#define TRGMODE_ENABLE (1 << 0)
#define SWTRGCMD_ENABLE (1 << 1)
/* Exynos3250, 3472, 4415, 5260 5410, 5420 and 5422 only supported. */
#define HWTRGEN_I80_RGB_ENABLE (1 << 3)
#define HWTRGMASK_I80_RGB_ENABLE (1 << 4)
#define HWTRGEN_ENABLE (1 << 3)
#define HWTRGMASK_ENABLE (1 << 4)
/* Exynos3250, 3472, 4415, 5260, 5420 and 5422 only supported. */
#define HWTRIGEN_PER_RGB_ENABLE (1 << 31)
#define HWTRIGEN_PER_ENABLE (1 << 31)
/* display mode change control register except exynos4 */
#define VIDOUT_CON 0x000
@ -420,16 +420,15 @@ static void fimd_setup_trigger(struct fimd_context *ctx)
u32 trg_type = ctx->driver_data->trg_type;
u32 val = readl(timing_base + TRIGCON);
val &= ~(TRGMODE_I80_RGB_ENABLE_I80);
val &= ~(TRGMODE_ENABLE);
if (trg_type == I80_HW_TRG) {
if (ctx->driver_data->has_hw_trigger)
val |= HWTRGEN_I80_RGB_ENABLE |
HWTRGMASK_I80_RGB_ENABLE;
val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
if (ctx->driver_data->has_trigger_per_te)
val |= HWTRIGEN_PER_RGB_ENABLE;
val |= HWTRIGEN_PER_ENABLE;
} else {
val |= TRGMODE_I80_RGB_ENABLE_I80;
val |= TRGMODE_ENABLE;
}
writel(val, timing_base + TRIGCON);
@ -879,7 +878,7 @@ static void fimd_trigger(struct device *dev)
atomic_set(&ctx->triggering, 1);
reg = readl(timing_base + TRIGCON);
reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
writel(reg, timing_base + TRIGCON);
/*

6
include/video/exynos5433_decon.h
View File

@ -179,9 +179,9 @@
#define TRIGCON_TRIGMODE_W1BUF (1 << 10)
#define TRIGCON_SWTRIGCMD_W0BUF (1 << 6)
#define TRIGCON_TRIGMODE_W0BUF (1 << 5)
#define TRIGCON_HWTRIGMASK_I80_RGB (1 << 4)
#define TRIGCON_HWTRIGEN_I80_RGB (1 << 3)
#define TRIGCON_HWTRIG_INV_I80_RGB (1 << 2)
#define TRIGCON_HWTRIGMASK (1 << 4)
#define TRIGCON_HWTRIGEN (1 << 3)
#define TRIGCON_HWTRIG_INV (1 << 2)
#define TRIGCON_SWTRIGCMD (1 << 1)
#define TRIGCON_SWTRIGEN (1 << 0)