drm/amdgpu: correct rlc save restore list initialization for v2_1
The save restore list initialization does not have to be pg guarded. And for some asic(e.g. Vega12), it does not have cntl/gpm/srm lists. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -648,7 +648,10 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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if (adev->gfx.rlc.is_rlc_v2_1) {
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if (adev->gfx.rlc.is_rlc_v2_1 &&
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adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
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adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
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adev->gfx.rlc.save_restore_list_srm_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
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info->fw = adev->gfx.rlc_fw;
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@ -2184,8 +2187,14 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
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{
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gfx_v9_0_init_csb(adev);
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if (!adev->gfx.rlc.is_rlc_v2_1)
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return;
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/*
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* Rlc save restore list is workable since v2_1.
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* And it's needed by gfxoff feature.
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*/
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if (adev->gfx.rlc.is_rlc_v2_1) {
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gfx_v9_1_init_rlc_save_restore_list(adev);
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gfx_v9_0_enable_save_restore_machine(adev);
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}
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if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
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AMD_PG_SUPPORT_GFX_SMG |
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@ -2193,9 +2202,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
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AMD_PG_SUPPORT_CP |
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AMD_PG_SUPPORT_GDS |
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AMD_PG_SUPPORT_RLC_SMU_HS)) {
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gfx_v9_1_init_rlc_save_restore_list(adev);
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gfx_v9_0_enable_save_restore_machine(adev);
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WREG32(mmRLC_JUMP_TABLE_RESTORE,
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adev->gfx.rlc.cp_table_gpu_addr >> 8);
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gfx_v9_0_init_gfx_power_gating(adev);
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