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drm/i915: Add Valleyview lane control definitions 

Added DPIO data lane register definitions for Valleyview

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Vijay Purushothaman 2012-09-27 19:13:03 +05:30 committed by Daniel Vetter
parent ae33cdcfc6
commit b56747aace
1 changed files with 8 additions and 0 deletions
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8
drivers/gpu/drm/i915/i915_reg.h
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@ -369,6 +369,7 @@
#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
#define DPIO_PLL_REFCLK_SEL_MASK 3
#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
#define _DPIO_REFSFR_B 0x8034
@ -384,6 +385,13 @@
#define DPIO_FASTCLK_DISABLE 0x8100
#define _DPIO_DATA_LANE0 0x0220
#define _DPIO_DATA_LANE1 0x0420
#define _DPIO_DATA_LANE2 0x2620
#define _DPIO_DATA_LANE3 0x2820
#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
/*
* Fence registers
*/