MIPS: Define __arch_swab64 for all mips r2 cpus
Some CPUs implement mipsr2, but because they are a super-set of mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into this category. We would still like to use the optimized implementation, so since we have already checked for CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of CONFIG_CPU_MIPS64_R2 is sufficient. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
27fdd325da
commit
b53d4d1f8d
|
@ -38,7 +38,11 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
|
||||||
}
|
}
|
||||||
#define __arch_swab32 __arch_swab32
|
#define __arch_swab32 __arch_swab32
|
||||||
|
|
||||||
#ifdef CONFIG_CPU_MIPS64_R2
|
/*
|
||||||
|
* Having already checked for CONFIG_CPU_MIPSR2, enable the
|
||||||
|
* optimized version for 64-bit kernel on r2 CPUs.
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
|
static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
|
||||||
{
|
{
|
||||||
__asm__(
|
__asm__(
|
||||||
|
@ -50,6 +54,6 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
|
||||||
return x;
|
return x;
|
||||||
}
|
}
|
||||||
#define __arch_swab64 __arch_swab64
|
#define __arch_swab64 __arch_swab64
|
||||||
#endif /* CONFIG_CPU_MIPS64_R2 */
|
#endif /* CONFIG_64BIT */
|
||||||
#endif /* CONFIG_CPU_MIPSR2 */
|
#endif /* CONFIG_CPU_MIPSR2 */
|
||||||
#endif /* _ASM_SWAB_H */
|
#endif /* _ASM_SWAB_H */
|
||||||
|
|
Loading…
Reference in New Issue