clk: qcom: ipq4019: correct sdcc frequency and parent name
1. The parent for sdcc clock is sdccpll. 2. The frequency value was wrong so modified the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -124,7 +124,7 @@ static struct parent_map gcc_xo_sdcc1_500_map[] = {
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static const char * const gcc_xo_sdcc1_500[] = {
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"xo",
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"ddrpll",
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"ddrpllsdcc",
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"fepll500",
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};
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@ -549,7 +549,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
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F(25000000, P_FEPLL500, 1, 1, 20),
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F(50000000, P_FEPLL500, 1, 1, 10),
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F(100000000, P_FEPLL500, 1, 1, 5),
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F(193000000, P_DDRPLL, 1, 0, 0),
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F(192000000, P_DDRPLL, 1, 0, 0),
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{ }
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};
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