usb: phy: samsung: Add PHY support for USB 3.0 controller
Adding PHY driver support for USB 3.0 controller for Samsung's SoCs. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Vivek Gautam
Felipe Balbi
parent
dc2377d0b0
commit
b527675817
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@ -61,3 +61,57 @@ Example:
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reg = <0x10020704 0x8>;
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};
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};
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** Samsung's usb 3.0 phy transceiver
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Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver
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which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0
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controllers across Samsung SOCs.
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Required properties:
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Exynos5250:
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- compatible : should be "samsung,exynos5250-usb3phy"
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- reg : base physical address of the phy registers and length of memory mapped
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region.
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- clocks: Clock IDs array as required by the controller.
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- clock-names: names of clocks correseponding to IDs in the clock property
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as requested by the controller driver.
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Optional properties:
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- #address-cells: should be '1' when usbphy node has a child node with 'reg'
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property.
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- #size-cells: should be '1' when usbphy node has a child node with 'reg'
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property.
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- ranges: allows valid translation between child's address space and parent's
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address space.
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- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
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interface for usb-phy. It should provide the following information required by
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usb-phy controller to control phy.
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- reg : base physical address of PHY_CONTROL registers.
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The size of this register is the total sum of size of all PHY_CONTROL
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registers that the SoC has. For example, the size will be
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'0x4' in case we have only one PHY_CONTROL register (e.g.
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OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
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and, '0x8' in case we have two PHY_CONTROL registers (e.g.
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USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
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and so on.
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Example:
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usbphy@12100000 {
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compatible = "samsung,exynos5250-usb3phy";
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reg = <0x12100000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&clock 1>, <&clock 286>;
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clock-names = "ext_xtal", "usbdrd30";
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usbphy-sys {
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/* USB device and host PHY_CONTROL registers */
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reg = <0x10040704 0x8>;
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};
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};
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@ -99,6 +99,13 @@ config SAMSUNG_USB2PHY
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Enable this to support Samsung USB 2.0 (High Speed) PHY controller
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driver for Samsung SoCs.
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config SAMSUNG_USB3PHY
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tristate "Samsung USB 3.0 PHY controller Driver"
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select SAMSUNG_USBPHY
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help
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Enable this to support Samsung USB 3.0 (Super Speed) phy controller
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for samsung SoCs.
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config TWL4030_USB
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tristate "TWL4030 USB Transceiver Driver"
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depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS
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@ -19,6 +19,7 @@ obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
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obj-$(CONFIG_OMAP_USB3) += phy-omap-usb3.o
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obj-$(CONFIG_SAMSUNG_USBPHY) += phy-samsung-usb.o
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obj-$(CONFIG_SAMSUNG_USB2PHY) += phy-samsung-usb2.o
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obj-$(CONFIG_SAMSUNG_USB3PHY) += phy-samsung-usb3.o
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obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
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obj-$(CONFIG_TWL6030_USB) += phy-twl6030-usb.o
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obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o
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@ -145,6 +145,86 @@
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#define EXYNOS5_PHY_OTG_TUNE (0x40)
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/* EXYNOS5: USB 3.0 DRD */
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#define EXYNOS5_DRD_LINKSYSTEM (0x04)
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#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
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#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
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#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
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#define EXYNOS5_DRD_PHYUTMI (0x08)
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#define PHYUTMI_OTGDISABLE (0x1 << 6)
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#define PHYUTMI_FORCESUSPEND (0x1 << 1)
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#define PHYUTMI_FORCESLEEP (0x1 << 0)
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#define EXYNOS5_DRD_PHYPIPE (0x0c)
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#define EXYNOS5_DRD_PHYCLKRST (0x10)
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#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
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#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
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#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
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#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
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#define PHYCLKRST_SSC_EN (0x1 << 20)
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#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
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#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
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#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
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#define PHYCLKRST_FSEL_MASK (0x3f << 5)
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#define PHYCLKRST_FSEL(_x) ((_x) << 5)
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#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
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#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
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#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
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#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
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#define PHYCLKRST_RETENABLEN (0x1 << 4)
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#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
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#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
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#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
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#define PHYCLKRST_PORTRESET (0x1 << 1)
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#define PHYCLKRST_COMMONONN (0x1 << 0)
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#define EXYNOS5_DRD_PHYREG0 (0x14)
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#define EXYNOS5_DRD_PHYREG1 (0x18)
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#define EXYNOS5_DRD_PHYPARAM0 (0x1c)
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#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
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#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
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#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
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#define EXYNOS5_DRD_PHYPARAM1 (0x20)
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#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
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#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
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#define EXYNOS5_DRD_PHYTERM (0x24)
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#define EXYNOS5_DRD_PHYTEST (0x28)
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#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
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#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
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#define EXYNOS5_DRD_PHYADP (0x2c)
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#define EXYNOS5_DRD_PHYBATCHG (0x30)
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#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
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#define EXYNOS5_DRD_PHYRESUME (0x34)
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#define EXYNOS5_DRD_LINKPORT (0x44)
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#ifndef MHZ
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#define MHZ (1000*1000)
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#endif
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@ -0,0 +1,349 @@
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/* linux/drivers/usb/phy/phy-samsung-usb3.c
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Vivek Gautam <gautam.vivek@samsung.com>
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*
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* Samsung USB 3.0 PHY transceiver; talks to DWC3 controller.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/usb/samsung_usb_phy.h>
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#include <linux/platform_data/samsung-usbphy.h>
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#include "phy-samsung-usb.h"
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/*
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* Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock core.
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*/
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static u32 samsung_usb3phy_set_refclk(struct samsung_usbphy *sphy)
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{
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u32 reg;
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u32 refclk;
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refclk = sphy->ref_clk_freq;
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reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
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PHYCLKRST_FSEL(refclk);
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switch (refclk) {
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case FSEL_CLKSEL_50M:
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x00));
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break;
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case FSEL_CLKSEL_20M:
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x00));
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break;
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case FSEL_CLKSEL_19200K:
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x88));
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break;
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case FSEL_CLKSEL_24M:
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default:
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
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PHYCLKRST_SSC_REFCLKSEL(0x88));
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break;
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}
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return reg;
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}
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static int samsung_exynos5_usb3phy_enable(struct samsung_usbphy *sphy)
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{
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void __iomem *regs = sphy->regs;
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u32 phyparam0;
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u32 phyparam1;
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u32 linksystem;
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u32 phybatchg;
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u32 phytest;
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u32 phyclkrst;
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/* Reset USB 3.0 PHY */
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writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
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phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0);
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/* Select PHY CLK source */
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phyparam0 &= ~PHYPARAM0_REF_USE_PAD;
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/* Set Loss-of-Signal Detector sensitivity */
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phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
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phyparam0 |= PHYPARAM0_REF_LOSLEVEL;
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writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0);
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writel(0x0, regs + EXYNOS5_DRD_PHYRESUME);
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/*
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* Setting the Frame length Adj value[6:1] to default 0x20
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* See xHCI 1.0 spec, 5.2.4
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*/
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linksystem = LINKSYSTEM_XHCI_VERSION_CONTROL |
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LINKSYSTEM_FLADJ(0x20);
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writel(linksystem, regs + EXYNOS5_DRD_LINKSYSTEM);
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phyparam1 = readl(regs + EXYNOS5_DRD_PHYPARAM1);
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/* Set Tx De-Emphasis level */
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phyparam1 &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
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phyparam1 |= PHYPARAM1_PCS_TXDEEMPH;
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writel(phyparam1, regs + EXYNOS5_DRD_PHYPARAM1);
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phybatchg = readl(regs + EXYNOS5_DRD_PHYBATCHG);
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phybatchg |= PHYBATCHG_UTMI_CLKSEL;
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writel(phybatchg, regs + EXYNOS5_DRD_PHYBATCHG);
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/* PHYTEST POWERDOWN Control */
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phytest = readl(regs + EXYNOS5_DRD_PHYTEST);
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phytest &= ~(PHYTEST_POWERDOWN_SSP |
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PHYTEST_POWERDOWN_HSP);
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writel(phytest, regs + EXYNOS5_DRD_PHYTEST);
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/* UTMI Power Control */
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writel(PHYUTMI_OTGDISABLE, regs + EXYNOS5_DRD_PHYUTMI);
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phyclkrst = samsung_usb3phy_set_refclk(sphy);
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phyclkrst |= PHYCLKRST_PORTRESET |
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/* Digital power supply in normal operating mode */
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PHYCLKRST_RETENABLEN |
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/* Enable ref clock for SS function */
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PHYCLKRST_REF_SSP_EN |
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/* Enable spread spectrum */
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PHYCLKRST_SSC_EN |
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/* Power down HS Bias and PLL blocks in suspend mode */
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PHYCLKRST_COMMONONN;
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writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
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udelay(10);
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phyclkrst &= ~(PHYCLKRST_PORTRESET);
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writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
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return 0;
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}
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static void samsung_exynos5_usb3phy_disable(struct samsung_usbphy *sphy)
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{
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u32 phyutmi;
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u32 phyclkrst;
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u32 phytest;
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void __iomem *regs = sphy->regs;
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phyutmi = PHYUTMI_OTGDISABLE |
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PHYUTMI_FORCESUSPEND |
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PHYUTMI_FORCESLEEP;
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writel(phyutmi, regs + EXYNOS5_DRD_PHYUTMI);
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/* Resetting the PHYCLKRST enable bits to reduce leakage current */
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phyclkrst = readl(regs + EXYNOS5_DRD_PHYCLKRST);
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phyclkrst &= ~(PHYCLKRST_REF_SSP_EN |
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PHYCLKRST_SSC_EN |
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PHYCLKRST_COMMONONN);
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writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST);
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/* Control PHYTEST to remove leakage current */
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phytest = readl(regs + EXYNOS5_DRD_PHYTEST);
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phytest |= (PHYTEST_POWERDOWN_SSP |
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PHYTEST_POWERDOWN_HSP);
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writel(phytest, regs + EXYNOS5_DRD_PHYTEST);
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}
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static int samsung_usb3phy_init(struct usb_phy *phy)
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{
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struct samsung_usbphy *sphy;
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unsigned long flags;
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int ret = 0;
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sphy = phy_to_sphy(phy);
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/* Enable the phy clock */
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ret = clk_prepare_enable(sphy->clk);
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if (ret) {
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dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
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return ret;
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}
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spin_lock_irqsave(&sphy->lock, flags);
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/* setting default phy-type for USB 3.0 */
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samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
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/* Disable phy isolation */
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samsung_usbphy_set_isolation(sphy, false);
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/* Initialize usb phy registers */
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samsung_exynos5_usb3phy_enable(sphy);
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spin_unlock_irqrestore(&sphy->lock, flags);
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/* Disable the phy clock */
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clk_disable_unprepare(sphy->clk);
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return ret;
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}
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/*
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* The function passed to the usb driver for phy shutdown
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*/
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static void samsung_usb3phy_shutdown(struct usb_phy *phy)
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{
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struct samsung_usbphy *sphy;
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unsigned long flags;
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sphy = phy_to_sphy(phy);
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if (clk_prepare_enable(sphy->clk)) {
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dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__);
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return;
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}
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spin_lock_irqsave(&sphy->lock, flags);
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/* setting default phy-type for USB 3.0 */
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samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE);
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/* De-initialize usb phy registers */
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samsung_exynos5_usb3phy_disable(sphy);
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/* Enable phy isolation */
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samsung_usbphy_set_isolation(sphy, true);
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spin_unlock_irqrestore(&sphy->lock, flags);
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clk_disable_unprepare(sphy->clk);
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}
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static int samsung_usb3phy_probe(struct platform_device *pdev)
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{
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struct samsung_usbphy *sphy;
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struct samsung_usbphy_data *pdata = pdev->dev.platform_data;
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struct device *dev = &pdev->dev;
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struct resource *phy_mem;
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void __iomem *phy_base;
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struct clk *clk;
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int ret;
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phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!phy_mem) {
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dev_err(dev, "%s: missing mem resource\n", __func__);
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return -ENODEV;
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}
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phy_base = devm_request_and_ioremap(dev, phy_mem);
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if (!phy_base) {
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dev_err(dev, "%s: register mapping failed\n", __func__);
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return -ENXIO;
|
||||
}
|
||||
|
||||
sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
|
||||
if (!sphy)
|
||||
return -ENOMEM;
|
||||
|
||||
clk = devm_clk_get(dev, "usbdrd30");
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(dev, "Failed to get device clock\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
sphy->dev = dev;
|
||||
|
||||
if (dev->of_node) {
|
||||
ret = samsung_usbphy_parse_dt(sphy);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
} else {
|
||||
if (!pdata) {
|
||||
dev_err(dev, "no platform data specified\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
sphy->plat = pdata;
|
||||
sphy->regs = phy_base;
|
||||
sphy->clk = clk;
|
||||
sphy->phy.dev = sphy->dev;
|
||||
sphy->phy.label = "samsung-usb3phy";
|
||||
sphy->phy.init = samsung_usb3phy_init;
|
||||
sphy->phy.shutdown = samsung_usb3phy_shutdown;
|
||||
sphy->drv_data = samsung_usbphy_get_driver_data(pdev);
|
||||
sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy);
|
||||
|
||||
spin_lock_init(&sphy->lock);
|
||||
|
||||
platform_set_drvdata(pdev, sphy);
|
||||
|
||||
return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB3);
|
||||
}
|
||||
|
||||
static int samsung_usb3phy_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct samsung_usbphy *sphy = platform_get_drvdata(pdev);
|
||||
|
||||
usb_remove_phy(&sphy->phy);
|
||||
|
||||
if (sphy->pmuregs)
|
||||
iounmap(sphy->pmuregs);
|
||||
if (sphy->sysreg)
|
||||
iounmap(sphy->sysreg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct samsung_usbphy_drvdata usb3phy_exynos5 = {
|
||||
.cpu_type = TYPE_EXYNOS5250,
|
||||
.devphy_en_mask = EXYNOS_USBPHY_ENABLE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id samsung_usbphy_dt_match[] = {
|
||||
{
|
||||
.compatible = "samsung,exynos5250-usb3phy",
|
||||
.data = &usb3phy_exynos5
|
||||
},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match);
|
||||
#endif
|
||||
|
||||
static struct platform_device_id samsung_usbphy_driver_ids[] = {
|
||||
{
|
||||
.name = "exynos5250-usb3phy",
|
||||
.driver_data = (unsigned long)&usb3phy_exynos5,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids);
|
||||
|
||||
static struct platform_driver samsung_usb3phy_driver = {
|
||||
.probe = samsung_usb3phy_probe,
|
||||
.remove = samsung_usb3phy_remove,
|
||||
.id_table = samsung_usbphy_driver_ids,
|
||||
.driver = {
|
||||
.name = "samsung-usb3phy",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(samsung_usbphy_dt_match),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(samsung_usb3phy_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Samsung USB 3.0 phy controller");
|
||||
MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:samsung-usb3phy");
|
||||
Loading…
Reference in New Issue