coresight: cti: Add sysfs access to program function registers
Adds in sysfs programming support for the CTI function register sets. Allows direct manipulation of channel / trigger association registers. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20200320165303.13681-4-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mike Leach
Greg Kroah-Hartman
parent
1a556ca6cc
commit
b5213376c2
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@ -122,4 +122,13 @@ config CORESIGHT_CTI
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halt compared to disabling sources and sinks normally in driver
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software.
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config CORESIGHT_CTI_INTEGRATION_REGS
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bool "Access CTI CoreSight Integration Registers"
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depends on CORESIGHT_CTI
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help
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This option adds support for the CoreSight integration registers on
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this device. The integration registers allow the exploration of the
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CTI trigger connections between this and other devices.These
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registers are not used in normal operation and can leave devices in
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an inconsistent state.
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endif
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@ -120,6 +120,361 @@ static struct attribute *coresight_cti_mgmt_attrs[] = {
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NULL,
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};
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/* CTI low level programming registers */
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/*
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* Show a simple 32 bit value if enabled and powered.
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* If inaccessible & pcached_val not NULL then show cached value.
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*/
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static ssize_t cti_reg32_show(struct device *dev, char *buf,
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u32 *pcached_val, int reg_offset)
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{
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u32 val = 0;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct cti_config *config = &drvdata->config;
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spin_lock(&drvdata->spinlock);
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if ((reg_offset >= 0) && cti_active(config)) {
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CS_UNLOCK(drvdata->base);
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val = readl_relaxed(drvdata->base + reg_offset);
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if (pcached_val)
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*pcached_val = val;
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CS_LOCK(drvdata->base);
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} else if (pcached_val) {
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val = *pcached_val;
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}
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spin_unlock(&drvdata->spinlock);
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return sprintf(buf, "%#x\n", val);
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}
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/*
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* Store a simple 32 bit value.
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* If pcached_val not NULL, then copy to here too,
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* if reg_offset >= 0 then write through if enabled.
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*/
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static ssize_t cti_reg32_store(struct device *dev, const char *buf,
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size_t size, u32 *pcached_val, int reg_offset)
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{
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unsigned long val;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct cti_config *config = &drvdata->config;
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if (kstrtoul(buf, 0, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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/* local store */
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if (pcached_val)
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*pcached_val = (u32)val;
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/* write through if offset and enabled */
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if ((reg_offset >= 0) && cti_active(config))
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cti_write_single_reg(drvdata, reg_offset, val);
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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/* Standard macro for simple rw cti config registers */
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#define cti_config_reg32_rw(name, cfgname, offset) \
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static ssize_t name##_show(struct device *dev, \
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struct device_attribute *attr, \
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char *buf) \
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{ \
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
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return cti_reg32_show(dev, buf, \
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&drvdata->config.cfgname, offset); \
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} \
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\
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static ssize_t name##_store(struct device *dev, \
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struct device_attribute *attr, \
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const char *buf, size_t size) \
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{ \
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
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return cti_reg32_store(dev, buf, size, \
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&drvdata->config.cfgname, offset); \
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} \
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static DEVICE_ATTR_RW(name)
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static ssize_t inout_sel_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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u32 val;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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val = (u32)drvdata->config.ctiinout_sel;
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return sprintf(buf, "%d\n", val);
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}
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static ssize_t inout_sel_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned long val;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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if (kstrtoul(buf, 0, &val))
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return -EINVAL;
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if (val > (CTIINOUTEN_MAX - 1))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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drvdata->config.ctiinout_sel = val;
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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static DEVICE_ATTR_RW(inout_sel);
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static ssize_t inen_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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unsigned long val;
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int index;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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spin_lock(&drvdata->spinlock);
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index = drvdata->config.ctiinout_sel;
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val = drvdata->config.ctiinen[index];
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spin_unlock(&drvdata->spinlock);
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return sprintf(buf, "%#lx\n", val);
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}
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static ssize_t inen_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned long val;
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int index;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct cti_config *config = &drvdata->config;
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if (kstrtoul(buf, 0, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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index = config->ctiinout_sel;
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config->ctiinen[index] = val;
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/* write through if enabled */
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if (cti_active(config))
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cti_write_single_reg(drvdata, CTIINEN(index), val);
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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static DEVICE_ATTR_RW(inen);
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static ssize_t outen_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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unsigned long val;
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int index;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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spin_lock(&drvdata->spinlock);
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index = drvdata->config.ctiinout_sel;
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val = drvdata->config.ctiouten[index];
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spin_unlock(&drvdata->spinlock);
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return sprintf(buf, "%#lx\n", val);
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}
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static ssize_t outen_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned long val;
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int index;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct cti_config *config = &drvdata->config;
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if (kstrtoul(buf, 0, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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index = config->ctiinout_sel;
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config->ctiouten[index] = val;
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/* write through if enabled */
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if (cti_active(config))
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cti_write_single_reg(drvdata, CTIOUTEN(index), val);
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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static DEVICE_ATTR_RW(outen);
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static ssize_t intack_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned long val;
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if (kstrtoul(buf, 0, &val))
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return -EINVAL;
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cti_write_intack(dev, val);
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return size;
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}
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static DEVICE_ATTR_WO(intack);
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cti_config_reg32_rw(gate, ctigate, CTIGATE);
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cti_config_reg32_rw(asicctl, asicctl, ASICCTL);
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cti_config_reg32_rw(appset, ctiappset, CTIAPPSET);
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static ssize_t appclear_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned long val;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct cti_config *config = &drvdata->config;
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if (kstrtoul(buf, 0, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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/* a 1'b1 in appclr clears down the same bit in appset*/
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config->ctiappset &= ~val;
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/* write through if enabled */
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if (cti_active(config))
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cti_write_single_reg(drvdata, CTIAPPCLEAR, val);
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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static DEVICE_ATTR_WO(appclear);
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static ssize_t apppulse_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned long val;
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct cti_config *config = &drvdata->config;
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if (kstrtoul(buf, 0, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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/* write through if enabled */
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if (cti_active(config))
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cti_write_single_reg(drvdata, CTIAPPPULSE, val);
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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static DEVICE_ATTR_WO(apppulse);
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coresight_cti_reg(triginstatus, CTITRIGINSTATUS);
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coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS);
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coresight_cti_reg(chinstatus, CTICHINSTATUS);
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coresight_cti_reg(choutstatus, CTICHOUTSTATUS);
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/*
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* Define CONFIG_CORESIGHT_CTI_INTEGRATION_REGS to enable the access to the
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* integration control registers. Normally only used to investigate connection
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* data.
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*/
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#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS
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/* macro to access RW registers with power check only (no enable check). */
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#define coresight_cti_reg_rw(name, offset) \
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static ssize_t name##_show(struct device *dev, \
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struct device_attribute *attr, char *buf) \
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{ \
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
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u32 val = 0; \
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pm_runtime_get_sync(dev->parent); \
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spin_lock(&drvdata->spinlock); \
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if (drvdata->config.hw_powered) \
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val = readl_relaxed(drvdata->base + offset); \
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spin_unlock(&drvdata->spinlock); \
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pm_runtime_put_sync(dev->parent); \
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return sprintf(buf, "0x%x\n", val); \
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} \
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\
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static ssize_t name##_store(struct device *dev, \
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struct device_attribute *attr, \
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const char *buf, size_t size) \
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{ \
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
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unsigned long val = 0; \
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if (kstrtoul(buf, 0, &val)) \
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return -EINVAL; \
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\
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pm_runtime_get_sync(dev->parent); \
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spin_lock(&drvdata->spinlock); \
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if (drvdata->config.hw_powered) \
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cti_write_single_reg(drvdata, offset, val); \
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spin_unlock(&drvdata->spinlock); \
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pm_runtime_put_sync(dev->parent); \
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return size; \
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} \
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static DEVICE_ATTR_RW(name)
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/* macro to access WO registers with power check only (no enable check). */
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#define coresight_cti_reg_wo(name, offset) \
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static ssize_t name##_store(struct device *dev, \
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struct device_attribute *attr, \
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const char *buf, size_t size) \
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{ \
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); \
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unsigned long val = 0; \
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if (kstrtoul(buf, 0, &val)) \
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return -EINVAL; \
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\
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pm_runtime_get_sync(dev->parent); \
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spin_lock(&drvdata->spinlock); \
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if (drvdata->config.hw_powered) \
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cti_write_single_reg(drvdata, offset, val); \
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spin_unlock(&drvdata->spinlock); \
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pm_runtime_put_sync(dev->parent); \
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return size; \
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} \
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static DEVICE_ATTR_WO(name)
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coresight_cti_reg_rw(itchout, ITCHOUT);
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coresight_cti_reg_rw(ittrigout, ITTRIGOUT);
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coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL);
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coresight_cti_reg_wo(itchinack, ITCHINACK);
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coresight_cti_reg_wo(ittriginack, ITTRIGINACK);
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coresight_cti_reg(ittrigin, ITTRIGIN);
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coresight_cti_reg(itchin, ITCHIN);
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coresight_cti_reg(itchoutack, ITCHOUTACK);
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coresight_cti_reg(ittrigoutack, ITTRIGOUTACK);
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#endif /* CORESIGHT_CTI_INTEGRATION_REGS */
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static struct attribute *coresight_cti_regs_attrs[] = {
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&dev_attr_inout_sel.attr,
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&dev_attr_inen.attr,
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&dev_attr_outen.attr,
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&dev_attr_gate.attr,
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&dev_attr_asicctl.attr,
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&dev_attr_intack.attr,
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&dev_attr_appset.attr,
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&dev_attr_appclear.attr,
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&dev_attr_apppulse.attr,
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&dev_attr_triginstatus.attr,
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&dev_attr_trigoutstatus.attr,
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&dev_attr_chinstatus.attr,
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&dev_attr_choutstatus.attr,
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#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS
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&dev_attr_itctrl.attr,
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&dev_attr_ittrigin.attr,
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&dev_attr_itchin.attr,
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&dev_attr_ittrigout.attr,
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&dev_attr_itchout.attr,
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&dev_attr_itchoutack.attr,
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&dev_attr_ittrigoutack.attr,
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&dev_attr_ittriginack.attr,
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&dev_attr_itchinack.attr,
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#endif
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NULL,
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};
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/* sysfs groups */
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static const struct attribute_group coresight_cti_group = {
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.attrs = coresight_cti_attrs,
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};
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@ -129,8 +484,14 @@ static const struct attribute_group coresight_cti_mgmt_group = {
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.name = "mgmt",
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};
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static const struct attribute_group coresight_cti_regs_group = {
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.attrs = coresight_cti_regs_attrs,
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.name = "regs",
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};
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const struct attribute_group *coresight_cti_groups[] = {
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&coresight_cti_group,
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&coresight_cti_mgmt_group,
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&coresight_cti_regs_group,
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NULL,
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};
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@ -149,6 +149,25 @@ cti_not_disabled:
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return 0;
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}
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void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value)
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{
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CS_UNLOCK(drvdata->base);
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writel_relaxed(value, drvdata->base + offset);
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CS_LOCK(drvdata->base);
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}
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void cti_write_intack(struct device *dev, u32 ackval)
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{
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struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct cti_config *config = &drvdata->config;
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spin_lock(&drvdata->spinlock);
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/* write if enabled */
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if (cti_active(config))
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cti_write_single_reg(drvdata, CTIINTACK, ackval);
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spin_unlock(&drvdata->spinlock);
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}
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/*
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* Look at the HW DEVID register for some of the HW settings.
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* DEVID[15:8] - max number of in / out triggers.
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@ -180,7 +180,15 @@ struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs,
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int out_sigs);
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int cti_enable(struct coresight_device *csdev);
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int cti_disable(struct coresight_device *csdev);
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void cti_write_intack(struct device *dev, u32 ackval);
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void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value);
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struct coresight_platform_data *
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coresight_cti_get_platform_data(struct device *dev);
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/* cti powered and enabled */
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static inline bool cti_active(struct cti_config *cfg)
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{
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return cfg->hw_powered && cfg->hw_enabled;
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}
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#endif /* _CORESIGHT_CORESIGHT_CTI_H */
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