nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated function
The i.MX7S/D has a different set of timing requirements, as a pre-cursor to
adding the i.MX7 timing parameters, move the i.MX6 stuff to a dedicated
function.
Fixes: 0642bac7da
("nvmem: imx-ocotp: add write support")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
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@ -168,33 +168,11 @@ read_end:
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return ret;
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}
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static int imx_ocotp_write(void *context, unsigned int offset, void *val,
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size_t bytes)
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static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
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{
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struct ocotp_priv *priv = context;
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u32 *buf = val;
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int ret;
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unsigned long clk_rate = 0;
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unsigned long strobe_read, relax, strobe_prog;
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u32 timing = 0;
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u32 ctrl;
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u8 waddr;
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u8 word = 0;
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/* allow only writing one complete OTP word at a time */
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if ((bytes != priv->config->word_size) ||
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(offset % priv->config->word_size))
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return -EINVAL;
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mutex_lock(&ocotp_mutex);
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ret = clk_prepare_enable(priv->clk);
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if (ret < 0) {
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mutex_unlock(&ocotp_mutex);
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dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
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return ret;
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}
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/* 47.3.1.3.1
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* Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
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@ -213,6 +191,35 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val,
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timing |= (strobe_read << 16) & 0x003F0000;
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writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
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}
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static int imx_ocotp_write(void *context, unsigned int offset, void *val,
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size_t bytes)
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{
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struct ocotp_priv *priv = context;
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u32 *buf = val;
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int ret;
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u32 ctrl;
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u8 waddr;
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u8 word = 0;
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/* allow only writing one complete OTP word at a time */
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if ((bytes != priv->config->word_size) ||
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(offset % priv->config->word_size))
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return -EINVAL;
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mutex_lock(&ocotp_mutex);
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ret = clk_prepare_enable(priv->clk);
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if (ret < 0) {
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mutex_unlock(&ocotp_mutex);
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dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
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return ret;
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}
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/* Setup the write timing values */
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imx_ocotp_set_imx6_timing(priv);
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/* 47.3.1.3.2
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* Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
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