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ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1 

We removed CLK_IGNORE_UNUSED from CLKID_SDIO's flag, so the sdhci0 and
sdhci1 don't work. We fix this by adding the optional 2nd clock for
BG2Q's sdhci0 and sdhci1. This patch brings another benefit: the 2nd
clock can be disabled during runtime pm, so saves power a bit.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This commit is contained in:
Jisheng Zhang 2015-12-07 21:09:25 +08:00 committed by Sebastian Hesselbarth
parent 5d756147f7
commit b5010d2081
1 changed files with 4 additions and 2 deletions
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6
arch/arm/boot/dts/berlin2q.dtsi
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@ -118,7 +118,8 @@
sdhci0: sdhci@ab0000 { sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc"; compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>; reg = <0xab0000 0x200>;
clocks = <&chip_clk CLKID_SDIO1XIN>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
}; };
@ -126,7 +127,8 @@
sdhci1: sdhci@ab0800 { sdhci1: sdhci@ab0800 {
compatible = "mrvl,pxav3-mmc"; compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>; reg = <0xab0800 0x200>;
clocks = <&chip_clk CLKID_SDIO1XIN>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
clock-names = "io", "core";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
}; };