[Blackfin] arch: fix bug - Make the MPU code aware of the async banks and the uncached DMA area.
Bug: CONFIG_MPU doesn't seem to handle access to ASYNC/IO Memory well http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3912 Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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@ -143,30 +143,39 @@ static noinline int dcplb_miss(void)
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unsigned long d_data;
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unsigned long d_data;
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nr_dcplb_miss++;
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nr_dcplb_miss++;
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if (addr >= _ramend)
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return CPLB_PROT_VIOL;
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d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
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d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
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#ifdef CONFIG_BFIN_DCACHE
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#ifdef CONFIG_BFIN_DCACHE
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d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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if (addr < _ramend - DMA_UNCACHED_REGION) {
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d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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#ifdef CONFIG_BFIN_WT
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#ifdef CONFIG_BFIN_WT
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d_data |= CPLB_L1_AOW | CPLB_WT;
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d_data |= CPLB_L1_AOW | CPLB_WT;
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#endif
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#endif
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#endif
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mask = current_rwx_mask;
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if (mask) {
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int page = addr >> PAGE_SHIFT;
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int offs = page >> 5;
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int bit = 1 << (page & 31);
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if (mask[offs] & bit)
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d_data |= CPLB_USER_RD;
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mask += page_mask_nelts;
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if (mask[offs] & bit)
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d_data |= CPLB_USER_WR;
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}
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}
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#endif
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if (addr >= _ramend) {
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if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
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&& (status & FAULT_USERSUPV)) {
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addr &= ~0x3fffff;
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d_data &= ~PAGE_SIZE_4KB;
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d_data |= PAGE_SIZE_4MB;
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} else
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return CPLB_PROT_VIOL;
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} else {
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mask = current_rwx_mask;
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if (mask) {
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int page = addr >> PAGE_SHIFT;
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int offs = page >> 5;
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int bit = 1 << (page & 31);
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if (mask[offs] & bit)
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d_data |= CPLB_USER_RD;
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mask += page_mask_nelts;
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if (mask[offs] & bit)
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d_data |= CPLB_USER_WR;
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}
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}
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idx = evict_one_dcplb();
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idx = evict_one_dcplb();
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addr &= PAGE_MASK;
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addr &= PAGE_MASK;
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@ -280,8 +289,7 @@ int cplb_hdr(int seqstat, struct pt_regs *regs)
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case 0x26:
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case 0x26:
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return dcplb_miss();
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return dcplb_miss();
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default:
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default:
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return 1;
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return 1;
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panic_cplb_error(seqstat, regs);
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}
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}
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}
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}
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