diff --git a/drivers/staging/ccree/cc_bitops.h b/drivers/staging/ccree/cc_bitops.h index ad3aeedb65e8..ee5238a9928d 100644 --- a/drivers/staging/ccree/cc_bitops.h +++ b/drivers/staging/ccree/cc_bitops.h @@ -32,31 +32,4 @@ (((new_val) & BITMASK(bit_size)) << (bit_offset)); \ } while (0) -/* Is val aligned to "align" ("align" must be power of 2) */ -#ifndef IS_ALIGNED -#define IS_ALIGNED(val, align) \ - (((uintptr_t)(val) & ((align) - 1)) == 0) -#endif - -#define SWAP_ENDIAN(word) \ - (((word) >> 24) | (((word) & 0x00FF0000) >> 8) | \ - (((word) & 0x0000FF00) << 8) | (((word) & 0x000000FF) << 24)) - -#ifdef BIG__ENDIAN -#define SWAP_TO_LE(word) SWAP_ENDIAN(word) -#define SWAP_TO_BE(word) word -#else -#define SWAP_TO_LE(word) word -#define SWAP_TO_BE(word) SWAP_ENDIAN(word) -#endif - - - -/* Is val a multiple of "mult" ("mult" must be power of 2) */ -#define IS_MULT(val, mult) \ - (((val) & ((mult) - 1)) == 0) - -#define IS_NULL_ADDR(adr) \ - (!(adr)) - #endif /*_CC_BITOPS_H_*/ diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h b/drivers/staging/ccree/cc_hw_queue_defs.h index 8dca344c15a3..537ea0dcab7c 100644 --- a/drivers/staging/ccree/cc_hw_queue_defs.h +++ b/drivers/staging/ccree/cc_hw_queue_defs.h @@ -17,7 +17,6 @@ #ifndef __CC_HW_QUEUE_DEFS_H__ #define __CC_HW_QUEUE_DEFS_H__ -#include "cc_pal_log.h" #include "cc_regs.h" #include "dx_crys_kernel.h" @@ -189,41 +188,6 @@ typedef enum HwDesKeySize { (pDesc)->word[5] = 0; \ } while (0) -/* HW descriptor debug functions */ -int createDetailedDump(HwDesc_s *pDesc); -void descriptor_log(HwDesc_s *desc); - -#if defined(HW_DESCRIPTOR_LOG) || defined(HW_DESC_DUMP_HOST_BUF) -#define LOG_HW_DESC(pDesc) descriptor_log(pDesc) -#else -#define LOG_HW_DESC(pDesc) -#endif - -#if (CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_TRACE) || defined(OEMFW_LOG) - -#ifdef UART_PRINTF -#define CREATE_DETAILED_DUMP(pDesc) createDetailedDump(pDesc) -#else -#define CREATE_DETAILED_DUMP(pDesc) -#endif - -#define HW_DESC_DUMP(pDesc) do { \ - CC_PAL_LOG_TRACE("\n---------------------------------------------------\n"); \ - CREATE_DETAILED_DUMP(pDesc); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[0]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[1]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[2]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[3]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[4]); \ - CC_PAL_LOG_TRACE("0x%08X\n", (unsigned int)(pDesc)->word[5]); \ - CC_PAL_LOG_TRACE("---------------------------------------------------\n\n"); \ -} while (0) - -#else -#define HW_DESC_DUMP(pDesc) do {} while (0) -#endif - - /*! * This macro indicates the end of current HW descriptors flow and release the HW engines. * diff --git a/drivers/staging/ccree/cc_pal_log.h b/drivers/staging/ccree/cc_pal_log.h deleted file mode 100644 index 21abd2d26b90..000000000000 --- a/drivers/staging/ccree/cc_pal_log.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#ifndef _CC_PAL_LOG_H_ -#define _CC_PAL_LOG_H_ - -#include "cc_pal_types.h" -#include "cc_pal_log_plat.h" - -/*! -@file -@brief This file contains the PAL layer log definitions, by default the log is disabled. -@defgroup cc_pal_log CryptoCell PAL logging APIs and definitions -@{ -@ingroup cc_pal -*/ - -/* PAL log levels (to be used in CC_PAL_logLevel) */ -/*! PAL log level - disabled. */ -#define CC_PAL_LOG_LEVEL_NULL (-1) /*!< \internal Disable logging */ -/*! PAL log level - error. */ -#define CC_PAL_LOG_LEVEL_ERR 0 -/*! PAL log level - warning. */ -#define CC_PAL_LOG_LEVEL_WARN 1 -/*! PAL log level - info. */ -#define CC_PAL_LOG_LEVEL_INFO 2 -/*! PAL log level - debug. */ -#define CC_PAL_LOG_LEVEL_DEBUG 3 -/*! PAL log level - trace. */ -#define CC_PAL_LOG_LEVEL_TRACE 4 -/*! PAL log level - data. */ -#define CC_PAL_LOG_LEVEL_DATA 5 - -#ifndef CC_PAL_LOG_CUR_COMPONENT -/* Setting default component mask in case caller did not define */ -/* (a mask that is always on for every log mask value but full masking) */ -/*! Default log debugged component.*/ -#define CC_PAL_LOG_CUR_COMPONENT 0xFFFFFFFF -#endif -#ifndef CC_PAL_LOG_CUR_COMPONENT_NAME -/*! Default log debugged component.*/ -#define CC_PAL_LOG_CUR_COMPONENT_NAME "CC" -#endif - -/* Select compile time log level (default if not explicitly specified by caller) */ -#ifndef CC_PAL_MAX_LOG_LEVEL /* Can be overriden by external definition of this constant */ -#ifdef DEBUG -/*! Default debug log level (when debug is set to on).*/ -#define CC_PAL_MAX_LOG_LEVEL CC_PAL_LOG_LEVEL_ERR /*CC_PAL_LOG_LEVEL_DEBUG*/ -#else /* Disable logging */ -/*! Default debug log level (when debug is set to on).*/ -#define CC_PAL_MAX_LOG_LEVEL CC_PAL_LOG_LEVEL_NULL -#endif -#endif /*CC_PAL_MAX_LOG_LEVEL*/ -/*! Evaluate CC_PAL_MAX_LOG_LEVEL in case provided by caller */ -#define __CC_PAL_LOG_LEVEL_EVAL(level) level -/*! Maximal log level defintion.*/ -#define _CC_PAL_MAX_LOG_LEVEL __CC_PAL_LOG_LEVEL_EVAL(CC_PAL_MAX_LOG_LEVEL) - - -#ifdef ARM_DSM -/*! Log init function. */ -#define CC_PalLogInit() do {} while (0) -/*! Log set level function - sets the level of logging in case of debug. */ -#define CC_PalLogLevelSet(setLevel) do {} while (0) -/*! Log set mask function - sets the component masking in case of debug. */ -#define CC_PalLogMaskSet(setMask) do {} while (0) -#else -#if _CC_PAL_MAX_LOG_LEVEL > CC_PAL_LOG_LEVEL_NULL -/*! Log init function. */ -void CC_PalLogInit(void); -/*! Log set level function - sets the level of logging in case of debug. */ -void CC_PalLogLevelSet(int setLevel); -/*! Log set mask function - sets the component masking in case of debug. */ -void CC_PalLogMaskSet(uint32_t setMask); -/*! Global variable for log level */ -extern int CC_PAL_logLevel; -/*! Global variable for log mask */ -extern uint32_t CC_PAL_logMask; -#else /* No log */ -/*! Log init function. */ -static inline void CC_PalLogInit(void) {} -/*! Log set level function - sets the level of logging in case of debug. */ -static inline void CC_PalLogLevelSet(int setLevel) {CC_UNUSED_PARAM(setLevel);} -/*! Log set mask function - sets the component masking in case of debug. */ -static inline void CC_PalLogMaskSet(uint32_t setMask) {CC_UNUSED_PARAM(setMask);} -#endif -#endif - -/*! Filter logging based on logMask and dispatch to platform specific logging mechanism. */ -#define _CC_PAL_LOG(level, format, ...) \ - if (CC_PAL_logMask & CC_PAL_LOG_CUR_COMPONENT) \ - __CC_PAL_LOG_PLAT(CC_PAL_LOG_LEVEL_ ## level, "%s:%s: " format, CC_PAL_LOG_CUR_COMPONENT_NAME, __func__, ##__VA_ARGS__) - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_ERR) -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_ERR(format, ... ) \ - _CC_PAL_LOG(ERR, format, ##__VA_ARGS__) -#else -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_ERR( ... ) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_WARN) -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_WARN(format, ... ) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_WARN) \ - _CC_PAL_LOG(WARN, format, ##__VA_ARGS__) -#else -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_WARN( ... ) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_INFO) -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_INFO(format, ... ) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_INFO) \ - _CC_PAL_LOG(INFO, format, ##__VA_ARGS__) -#else -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_INFO( ... ) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_DEBUG) -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_DEBUG(format, ... ) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_DEBUG) \ - _CC_PAL_LOG(DEBUG, format, ##__VA_ARGS__) - -/*! Log message buffer.*/ -#define CC_PAL_LOG_DUMP_BUF(msg, buf, size) \ - do { \ - int i; \ - uint8_t *pData = (uint8_t*)buf; \ - \ - PRINTF("%s (%d):\n", msg, size); \ - for (i = 0; i < size; i++) { \ - PRINTF("0x%02X ", pData[i]); \ - if ((i & 0xF) == 0xF) { \ - PRINTF("\n"); \ - } \ - } \ - PRINTF("\n"); \ - } while (0) -#else -/*! Log debug messages.*/ -#define CC_PAL_LOG_DEBUG( ... ) do {} while (0) -/*! Log debug buffer.*/ -#define CC_PAL_LOG_DUMP_BUF(msg, buf, size) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_TRACE) -/*! Log debug trace.*/ -#define CC_PAL_LOG_TRACE(format, ... ) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_TRACE) \ - _CC_PAL_LOG(TRACE, format, ##__VA_ARGS__) -#else -/*! Log debug trace.*/ -#define CC_PAL_LOG_TRACE(...) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_TRACE) -/*! Log debug data.*/ -#define CC_PAL_LOG_DATA(format, ...) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_TRACE) \ - _CC_PAL_LOG(DATA, format, ##__VA_ARGS__) -#else -/*! Log debug data.*/ -#define CC_PAL_LOG_DATA( ...) do {} while (0) -#endif -/** -@} - */ - -#endif /*_CC_PAL_LOG_H_*/ diff --git a/drivers/staging/ccree/cc_pal_log_plat.h b/drivers/staging/ccree/cc_pal_log_plat.h deleted file mode 100644 index bc47a50e1917..000000000000 --- a/drivers/staging/ccree/cc_pal_log_plat.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -/* Dummy pal_log_plat for test driver in kernel */ - -#ifndef _SSI_PAL_LOG_PLAT_H_ -#define _SSI_PAL_LOG_PLAT_H_ - -#if defined(DEBUG) - -#define __CC_PAL_LOG_PLAT(level, format, ...) printk(level "cc7x_test::" format , ##__VA_ARGS__) - -#else /* Disable all prints */ - -#define __CC_PAL_LOG_PLAT(...) do {} while (0) - -#endif - -#endif /*_SASI_PAL_LOG_PLAT_H_*/ - diff --git a/drivers/staging/ccree/cc_pal_types.h b/drivers/staging/ccree/cc_pal_types.h deleted file mode 100644 index bf8a5e122992..000000000000 --- a/drivers/staging/ccree/cc_pal_types.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#ifndef CC_PAL_TYPES_H -#define CC_PAL_TYPES_H - -/*! -@file -@brief This file contains platform-dependent definitions and types. -@defgroup cc_pal_types CryptoCell PAL platform dependant types -@{ -@ingroup cc_pal - -*/ - -#include "cc_pal_types_plat.h" - -/*! Boolean definition.*/ -typedef enum { - /*! Boolean false definition.*/ - CC_FALSE = 0, - /*! Boolean true definition.*/ - CC_TRUE = 1 -} CCBool; - -/*! Success definition. */ -#define CC_SUCCESS 0UL -/*! Failure definition. */ -#define CC_FAIL 1UL - -/*! Defintion of 1KB in bytes. */ -#define CC_1K_SIZE_IN_BYTES 1024 -/*! Defintion of number of bits in a byte. */ -#define CC_BITS_IN_BYTE 8 -/*! Defintion of number of bits in a 32bits word. */ -#define CC_BITS_IN_32BIT_WORD 32 -/*! Defintion of number of bytes in a 32bits word. */ -#define CC_32BIT_WORD_SIZE (sizeof(uint32_t)) - -/*! Success (OK) defintion. */ -#define CC_OK 0 - -/*! Macro that handles unused parameters in the code (to avoid compilation warnings). */ -#define CC_UNUSED_PARAM(prm) ((void)prm) - -/*! Maximal uint32 value.*/ -#define CC_MAX_UINT32_VAL (0xFFFFFFFF) - - -/* Minimum and Maximum macros */ -#ifdef min -/*! Definition for minimum. */ -#define CC_MIN(a,b) min( a , b ) -#else -/*! Definition for minimum. */ -#define CC_MIN( a , b ) ( ( (a) < (b) ) ? (a) : (b) ) -#endif - -#ifdef max -/*! Definition for maximum. */ -#define CC_MAX(a,b) max( a , b ) -#else -/*! Definition for maximum. */ -#define CC_MAX( a , b ) ( ( (a) > (b) ) ? (a) : (b) ) -#endif - -/*! Macro that calculates number of full bytes from bits (i.e. 7 bits are 1 byte). */ -#define CALC_FULL_BYTES(numBits) ((numBits)/CC_BITS_IN_BYTE + (((numBits) & (CC_BITS_IN_BYTE-1)) > 0)) -/*! Macro that calculates number of full 32bits words from bits (i.e. 31 bits are 1 word). */ -#define CALC_FULL_32BIT_WORDS(numBits) ((numBits)/CC_BITS_IN_32BIT_WORD + (((numBits) & (CC_BITS_IN_32BIT_WORD-1)) > 0)) -/*! Macro that calculates number of full 32bits words from bytes (i.e. 3 bytes are 1 word). */ -#define CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) ((sizeBytes)/CC_32BIT_WORD_SIZE + (((sizeBytes) & (CC_32BIT_WORD_SIZE-1)) > 0)) -/*! Macro that round up bits to 32bits words. */ -#define ROUNDUP_BITS_TO_32BIT_WORD(numBits) (CALC_FULL_32BIT_WORDS(numBits) * CC_BITS_IN_32BIT_WORD) -/*! Macro that round up bits to bytes. */ -#define ROUNDUP_BITS_TO_BYTES(numBits) (CALC_FULL_BYTES(numBits) * CC_BITS_IN_BYTE) -/*! Macro that round up bytes to 32bits words. */ -#define ROUNDUP_BYTES_TO_32BIT_WORD(sizeBytes) (CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) * CC_32BIT_WORD_SIZE) - - -/** -@} - */ -#endif diff --git a/drivers/staging/ccree/cc_pal_types_plat.h b/drivers/staging/ccree/cc_pal_types_plat.h deleted file mode 100644 index b682ff0e40e6..000000000000 --- a/drivers/staging/ccree/cc_pal_types_plat.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - - -#ifndef SSI_PAL_TYPES_PLAT_H -#define SSI_PAL_TYPES_PLAT_H -/* Linux kernel types */ - -#include - -#ifndef NULL /* Missing in Linux kernel */ -#define NULL (0x0L) -#endif - - -#endif /*SSI_PAL_TYPES_PLAT_H*/ diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h index a2d42a368335..e81b0dc8ce5e 100644 --- a/drivers/staging/ccree/cc_regs.h +++ b/drivers/staging/ccree/cc_regs.h @@ -32,9 +32,6 @@ #define CC_REG_BIT_SHIFT(reg_name, field_name) \ (DX_ ## reg_name ## _ ## field_name ## _BIT_SHIFT) -/* Register Offset macros (from registers base address in host) */ -#include "dx_reg_base_host.h" - /* Read-Modify-Write a field of a register */ #define MODIFY_REGISTER_FLD(unitName, regName, fldName, fldVal) \ do { \ @@ -44,14 +41,6 @@ do { \ WRITE_REGISTER(CC_REG_ADDR(unitName, regName), regVal); \ } while (0) -/* Registers address macros for ENV registers (development FPGA only) */ -#ifdef DX_BASE_ENV_REGS - -/* This offset should be added to mapping address of DX_BASE_ENV_REGS */ -#define CC_ENV_REG_OFFSET(reg_name) (DX_ENV_ ## reg_name ## _REG_OFFSET) - -#endif /*DX_BASE_ENV_REGS*/ - /*! Bit fields get */ #define CC_REG_FLD_GET(unit_name, reg_name, fld_name, reg_val) \ (DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \ diff --git a/drivers/staging/ccree/dx_env.h b/drivers/staging/ccree/dx_env.h deleted file mode 100644 index d4c0440131e0..000000000000 --- a/drivers/staging/ccree/dx_env.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#ifndef __DX_ENV_H__ -#define __DX_ENV_H__ - -// -------------------------------------- -// BLOCK: FPGA_ENV_REGS -// -------------------------------------- -#define DX_ENV_PKA_DEBUG_MODE_REG_OFFSET 0x024UL -#define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_SCAN_MODE_REG_OFFSET 0x030UL -#define DX_ENV_SCAN_MODE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SCAN_MODE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_ALLOW_SCAN_REG_OFFSET 0x034UL -#define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_HOST_INT_REG_OFFSET 0x0A0UL -#define DX_ENV_CC_HOST_INT_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_HOST_INT_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_PUB_HOST_INT_REG_OFFSET 0x0A4UL -#define DX_ENV_CC_PUB_HOST_INT_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_PUB_HOST_INT_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_RST_N_REG_OFFSET 0x0A8UL -#define DX_ENV_CC_RST_N_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_RST_N_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_RST_OVERRIDE_REG_OFFSET 0x0ACUL -#define DX_ENV_RST_OVERRIDE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_RST_OVERRIDE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_POR_N_ADDR_REG_OFFSET 0x0E0UL -#define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_COLD_RST_REG_OFFSET 0x0FCUL -#define DX_ENV_CC_COLD_RST_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_COLD_RST_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_DUMMY_ADDR_REG_OFFSET 0x108UL -#define DX_ENV_DUMMY_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_DUMMY_ADDR_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_COUNTER_CLR_REG_OFFSET 0x118UL -#define DX_ENV_COUNTER_CLR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_COUNTER_CLR_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_COUNTER_RD_REG_OFFSET 0x11CUL -#define DX_ENV_COUNTER_RD_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_COUNTER_RD_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_RNG_DEBUG_ENABLE_REG_OFFSET 0x430UL -#define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_LCS_REG_OFFSET 0x43CUL -#define DX_ENV_CC_LCS_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_LCS_VALUE_BIT_SIZE 0x8UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_REG_OFFSET 0x440UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SHIFT 0x0UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SIZE 0x1UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SHIFT 0x1UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SIZE 0x1UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SHIFT 0x2UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SIZE 0x1UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SHIFT 0x3UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SIZE 0x1UL -#define DX_ENV_DCU_EN_REG_OFFSET 0x444UL -#define DX_ENV_DCU_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_DCU_EN_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_CC_LCS_IS_VALID_REG_OFFSET 0x448UL -#define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_POWER_DOWN_REG_OFFSET 0x478UL -#define DX_ENV_POWER_DOWN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_POWER_DOWN_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_DCU_H_EN_REG_OFFSET 0x484UL -#define DX_ENV_DCU_H_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_DCU_H_EN_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_VERSION_REG_OFFSET 0x488UL -#define DX_ENV_VERSION_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_VERSION_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_ROSC_WRITE_REG_OFFSET 0x48CUL -#define DX_ENV_ROSC_WRITE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_ROSC_WRITE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_ROSC_ADDR_REG_OFFSET 0x490UL -#define DX_ENV_ROSC_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_ROSC_ADDR_VALUE_BIT_SIZE 0x8UL -#define DX_ENV_RESET_SESSION_KEY_REG_OFFSET 0x494UL -#define DX_ENV_RESET_SESSION_KEY_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_RESET_SESSION_KEY_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_SESSION_KEY_0_REG_OFFSET 0x4A0UL -#define DX_ENV_SESSION_KEY_0_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_0_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_SESSION_KEY_1_REG_OFFSET 0x4A4UL -#define DX_ENV_SESSION_KEY_1_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_1_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_SESSION_KEY_2_REG_OFFSET 0x4A8UL -#define DX_ENV_SESSION_KEY_2_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_2_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_SESSION_KEY_3_REG_OFFSET 0x4ACUL -#define DX_ENV_SESSION_KEY_3_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_3_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_SESSION_KEY_VALID_REG_OFFSET 0x4B0UL -#define DX_ENV_SESSION_KEY_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_SPIDEN_REG_OFFSET 0x4D0UL -#define DX_ENV_SPIDEN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SPIDEN_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_AXIM_USER_PARAMS_REG_OFFSET 0x600UL -#define DX_ENV_AXIM_USER_PARAMS_ARUSER_BIT_SHIFT 0x0UL -#define DX_ENV_AXIM_USER_PARAMS_ARUSER_BIT_SIZE 0x5UL -#define DX_ENV_AXIM_USER_PARAMS_AWUSER_BIT_SHIFT 0x5UL -#define DX_ENV_AXIM_USER_PARAMS_AWUSER_BIT_SIZE 0x5UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_REG_OFFSET 0x604UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_BIT_BIT_SHIFT 0x0UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_BIT_BIT_SIZE 0x1UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_OVERRIDE_BIT_SHIFT 0x1UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_OVERRIDE_BIT_SIZE 0x1UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_BIT_BIT_SHIFT 0x2UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_BIT_BIT_SIZE 0x1UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_OVERRIDE_BIT_SHIFT 0x3UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_OVERRIDE_BIT_SIZE 0x1UL -#define DX_ENV_AO_CC_KPLT_0_REG_OFFSET 0x620UL -#define DX_ENV_AO_CC_KPLT_0_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KPLT_0_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KPLT_1_REG_OFFSET 0x624UL -#define DX_ENV_AO_CC_KPLT_1_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KPLT_1_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KPLT_2_REG_OFFSET 0x628UL -#define DX_ENV_AO_CC_KPLT_2_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KPLT_2_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KPLT_3_REG_OFFSET 0x62CUL -#define DX_ENV_AO_CC_KPLT_3_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KPLT_3_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KCST_0_REG_OFFSET 0x630UL -#define DX_ENV_AO_CC_KCST_0_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KCST_0_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KCST_1_REG_OFFSET 0x634UL -#define DX_ENV_AO_CC_KCST_1_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KCST_1_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KCST_2_REG_OFFSET 0x638UL -#define DX_ENV_AO_CC_KCST_2_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KCST_2_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KCST_3_REG_OFFSET 0x63CUL -#define DX_ENV_AO_CC_KCST_3_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KCST_3_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APB_FIPS_ADDR_REG_OFFSET 0x650UL -#define DX_ENV_APB_FIPS_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_ADDR_VALUE_BIT_SIZE 0xCUL -#define DX_ENV_APB_FIPS_VAL_REG_OFFSET 0x654UL -#define DX_ENV_APB_FIPS_VAL_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_VAL_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APB_FIPS_MASK_REG_OFFSET 0x658UL -#define DX_ENV_APB_FIPS_MASK_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_MASK_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APB_FIPS_CNT_REG_OFFSET 0x65CUL -#define DX_ENV_APB_FIPS_CNT_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_CNT_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APB_FIPS_NEW_ADDR_REG_OFFSET 0x660UL -#define DX_ENV_APB_FIPS_NEW_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_NEW_ADDR_VALUE_BIT_SIZE 0xCUL -#define DX_ENV_APB_FIPS_NEW_VAL_REG_OFFSET 0x664UL -#define DX_ENV_APB_FIPS_NEW_VAL_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_NEW_VAL_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APBP_FIPS_ADDR_REG_OFFSET 0x670UL -#define DX_ENV_APBP_FIPS_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_ADDR_VALUE_BIT_SIZE 0xCUL -#define DX_ENV_APBP_FIPS_VAL_REG_OFFSET 0x674UL -#define DX_ENV_APBP_FIPS_VAL_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_VAL_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APBP_FIPS_MASK_REG_OFFSET 0x678UL -#define DX_ENV_APBP_FIPS_MASK_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_MASK_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APBP_FIPS_CNT_REG_OFFSET 0x67CUL -#define DX_ENV_APBP_FIPS_CNT_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_CNT_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APBP_FIPS_NEW_ADDR_REG_OFFSET 0x680UL -#define DX_ENV_APBP_FIPS_NEW_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_NEW_ADDR_VALUE_BIT_SIZE 0xCUL -#define DX_ENV_APBP_FIPS_NEW_VAL_REG_OFFSET 0x684UL -#define DX_ENV_APBP_FIPS_NEW_VAL_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_NEW_VAL_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_CC_POWERDOWN_EN_REG_OFFSET 0x690UL -#define DX_ENV_CC_POWERDOWN_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_POWERDOWN_EN_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_POWERDOWN_RST_EN_REG_OFFSET 0x694UL -#define DX_ENV_CC_POWERDOWN_RST_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_POWERDOWN_RST_EN_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_POWERDOWN_RST_CNTR_REG_OFFSET 0x698UL -#define DX_ENV_POWERDOWN_RST_CNTR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_POWERDOWN_RST_CNTR_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_POWERDOWN_EN_DEBUG_REG_OFFSET 0x69CUL -#define DX_ENV_POWERDOWN_EN_DEBUG_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_POWERDOWN_EN_DEBUG_VALUE_BIT_SIZE 0x1UL -// -------------------------------------- -// BLOCK: ENV_CC_MEMORIES -// -------------------------------------- -#define DX_ENV_FUSE_READY_REG_OFFSET 0x000UL -#define DX_ENV_FUSE_READY_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_FUSE_READY_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_PERF_RAM_MASTER_REG_OFFSET 0x0ECUL -#define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_PERF_RAM_ADDR_HIGH4_REG_OFFSET 0x0F0UL -#define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SIZE 0x2UL -#define DX_ENV_FUSES_RAM_REG_OFFSET 0x3ECUL -#define DX_ENV_FUSES_RAM_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_FUSES_RAM_VALUE_BIT_SIZE 0x20UL -// -------------------------------------- -// BLOCK: ENV_PERF_RAM_BASE -// -------------------------------------- -#define DX_ENV_PERF_RAM_BASE_REG_OFFSET 0x000UL -#define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SIZE 0x20UL - -#endif /*__DX_ENV_H__*/ diff --git a/drivers/staging/ccree/dx_reg_base_host.h b/drivers/staging/ccree/dx_reg_base_host.h index ffe45dded17f..47bbadbcd1df 100644 --- a/drivers/staging/ccree/dx_reg_base_host.h +++ b/drivers/staging/ccree/dx_reg_base_host.h @@ -17,16 +17,7 @@ #ifndef __DX_REG_BASE_HOST_H__ #define __DX_REG_BASE_HOST_H__ -/* Identify platform: Xilinx Zynq7000 ZC706 */ -#define DX_PLAT_ZYNQ7000 1 -#define DX_PLAT_ZYNQ7000_ZC706 1 - #define DX_BASE_CC 0x80000000 - -#define DX_BASE_ENV_REGS 0x40008000 -#define DX_BASE_ENV_CC_MEMORIES 0x40008000 -#define DX_BASE_ENV_PERF_RAM 0x40009000 - #define DX_BASE_HOST_RGF 0x0UL #define DX_BASE_CRY_KERNEL 0x0UL #define DX_BASE_ROM 0x40000000 diff --git a/drivers/staging/ccree/hw_queue_defs_plat.h b/drivers/staging/ccree/hw_queue_defs_plat.h deleted file mode 100644 index bcca509e2549..000000000000 --- a/drivers/staging/ccree/hw_queue_defs_plat.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#ifndef __HW_QUEUE_DEFS_PLAT_H__ -#define __HW_QUEUE_DEFS_PLAT_H__ - - -/*****************************/ -/* Descriptor packing macros */ -/*****************************/ - -#define HW_QUEUE_FREE_SLOTS_GET() (CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_CONTENT)) & HW_QUEUE_SLOTS_MAX) - -#define HW_QUEUE_POLL_QUEUE_UNTIL_FREE_SLOTS(seqLen) \ - do { \ - } while (HW_QUEUE_FREE_SLOTS_GET() < (seqLen)) - -#define HW_DESC_PUSH_TO_QUEUE(pDesc) do { \ - LOG_HW_DESC(pDesc); \ - HW_DESC_DUMP(pDesc); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(0), (pDesc)->word[0]); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(1), (pDesc)->word[1]); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(2), (pDesc)->word[2]); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(3), (pDesc)->word[3]); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(4), (pDesc)->word[4]); \ - wmb(); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(5), (pDesc)->word[5]); \ -} while (0) - -#endif /*__HW_QUEUE_DEFS_PLAT_H__*/ diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index 5f1070801d54..d3e9eb2dcbf6 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -136,9 +136,6 @@ struct ssi_drvdata { struct resource *res_mem; struct resource *res_irq; void __iomem *cc_base; -#ifdef DX_BASE_ENV_REGS - void __iomem *env_base; /* ARM CryptoCell development FPGAs only */ -#endif unsigned int irq; uint32_t irq_mask; uint32_t fw_ver;