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irqchip/gic: Drop support for secondary GIC in non-DT systems 

We do not have any in-tree platform with this pathological setup,
and only a single system (Cavium's cns3xxx) isn't DT aware.

Let's drop the secondary GIC support for now, until we remove
the above horror altogether.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Marc Zyngier 2019-03-11 15:38:10 +00:00
parent 7d3a5eb78e
commit b41fdc4a7b
3 changed files with 18 additions and 32 deletions
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2
arch/arm/mach-cns3xxx/core.c
View File

@ -90,7 +90,7 @@ void __init cns3xxx_map_io(void)
/* used by entry-macro.S */ /* used by entry-macro.S */
void __init cns3xxx_init_irq(void) void __init cns3xxx_init_irq(void)
{ {
gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
} }

45
drivers/irqchip/irq-gic.c
View File

@ -1089,11 +1089,10 @@ static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
#endif #endif
} }
static int gic_init_bases(struct gic_chip_data *gic, int irq_start, static int gic_init_bases(struct gic_chip_data *gic,
struct fwnode_handle *handle) struct fwnode_handle *handle)
{ {
irq_hw_number_t hwirq_base; int gic_irqs, ret;
int gic_irqs, irq_base, ret;
if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
/* Frankein-GIC without banked registers... */ /* Frankein-GIC without banked registers... */
@ -1145,28 +1144,21 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
} else { /* Legacy support */ } else { /* Legacy support */
/* /*
* For primary GICs, skip over SGIs. * For primary GICs, skip over SGIs.
* For secondary GICs, skip over PPIs, too. * No secondary GIC support whatsoever.
*/ */
if (gic == &gic_data[0] && (irq_start & 31) > 0) { int irq_base;
hwirq_base = 16;
if (irq_start != -1)
irq_start = (irq_start & ~31) + 16;
} else {
hwirq_base = 32;
}
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ gic_irqs -= 16; /* calculate # of irqs to allocate */
irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, irq_base = irq_alloc_descs(16, 16, gic_irqs,
numa_node_id()); numa_node_id());
if (irq_base < 0) { if (irq_base < 0) {
WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
irq_start); irq_base = 16;
irq_base = irq_start;
} }
gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
hwirq_base, &gic_irq_domain_ops, gic); 16, &gic_irq_domain_ops, gic);
} }
if (WARN_ON(!gic->domain)) { if (WARN_ON(!gic->domain)) {
@ -1195,7 +1187,6 @@ error:
} }
static int __init __gic_init_bases(struct gic_chip_data *gic, static int __init __gic_init_bases(struct gic_chip_data *gic,
int irq_start,
struct fwnode_handle *handle) struct fwnode_handle *handle)
{ {
char *name; char *name;
@ -1231,32 +1222,28 @@ static int __init __gic_init_bases(struct gic_chip_data *gic,
gic_init_chip(gic, NULL, name, false); gic_init_chip(gic, NULL, name, false);
} }
ret = gic_init_bases(gic, irq_start, handle); ret = gic_init_bases(gic, handle);
if (ret) if (ret)
kfree(name); kfree(name);
return ret; return ret;
} }
void __init gic_init(unsigned int gic_nr, int irq_start, void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
void __iomem *dist_base, void __iomem *cpu_base)
{ {
struct gic_chip_data *gic; struct gic_chip_data *gic;
if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR))
return;
/* /*
* Non-DT/ACPI systems won't run a hypervisor, so let's not * Non-DT/ACPI systems won't run a hypervisor, so let's not
* bother with these... * bother with these...
*/ */
static_branch_disable(&supports_deactivate_key); static_branch_disable(&supports_deactivate_key);
gic = &gic_data[gic_nr]; gic = &gic_data[0];
gic->raw_dist_base = dist_base; gic->raw_dist_base = dist_base;
gic->raw_cpu_base = cpu_base; gic->raw_cpu_base = cpu_base;
__gic_init_bases(gic, irq_start, NULL); __gic_init_bases(gic, NULL);
} }
static void gic_teardown(struct gic_chip_data *gic) static void gic_teardown(struct gic_chip_data *gic)
@ -1399,7 +1386,7 @@ int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
if (ret) if (ret)
return ret; return ret;
ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode); ret = gic_init_bases(*gic, &dev->of_node->fwnode);
if (ret) { if (ret) {
gic_teardown(*gic); gic_teardown(*gic);
return ret; return ret;
@ -1459,7 +1446,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
static_branch_disable(&supports_deactivate_key); static_branch_disable(&supports_deactivate_key);
ret = __gic_init_bases(gic, -1, &node->fwnode); ret = __gic_init_bases(gic, &node->fwnode);
if (ret) { if (ret) {
gic_teardown(gic); gic_teardown(gic);
return ret; return ret;
@ -1650,7 +1637,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
return -ENOMEM; return -ENOMEM;
} }
ret = __gic_init_bases(gic, -1, domain_handle); ret = __gic_init_bases(gic, domain_handle);
if (ret) { if (ret) {
pr_err("Failed to initialise GIC\n"); pr_err("Failed to initialise GIC\n");
irq_domain_free_fwnode(domain_handle); irq_domain_free_fwnode(domain_handle);

3
include/linux/irqchip/arm-gic.h
View File

@ -158,8 +158,7 @@ int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);
* Legacy platforms not converted to DT yet must use this to init * Legacy platforms not converted to DT yet must use this to init
* their GIC * their GIC
*/ */
void gic_init(unsigned int nr, int start, void gic_init(void __iomem *dist , void __iomem *cpu);
void __iomem *dist , void __iomem *cpu);
int gicv2m_init(struct fwnode_handle *parent_handle, int gicv2m_init(struct fwnode_handle *parent_handle,
struct irq_domain *parent); struct irq_domain *parent);