TULIP: Fix for 64-bit MIPS
From: Jim Gifford <maillist@jg555.com>, Grant Grundler <grundler@parisc-linux.org>, Peter Horton <pdh@colonel-panic.org> With Grant's help I was able to get the tulip driver to work with 64 bit MIPS. [VAL: I'm happy with the 1.5 ms max delay; it doesn't seem excessive.] Signed-off-by: Valerie Henson <val_henson@linux.intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Cc: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -44,8 +44,10 @@ static const unsigned char comet_miireg2offset[32] = {
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/* MII transceiver control section.
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Read and write the MII registers using software-generated serial
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MDIO protocol. See the MII specifications or DP83840A data sheet
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for details. */
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MDIO protocol.
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See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
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or DP83840A data sheet for more details.
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*/
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int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
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{
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@ -272,13 +274,29 @@ void tulip_select_media(struct net_device *dev, int startup)
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int reset_length = p[2 + init_length];
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misc_info = (u16*)(reset_sequence + reset_length);
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if (startup) {
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int timeout = 10; /* max 1 ms */
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iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
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for (i = 0; i < reset_length; i++)
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iowrite32(reset_sequence[i], ioaddr + CSR12);
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/* flush posted writes */
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ioread32(ioaddr + CSR12);
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/* Sect 3.10.3 in DP83840A.pdf (p39) */
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udelay(500);
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/* Section 4.2 in DP83840A.pdf (p43) */
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/* and IEEE 802.3 "22.2.4.1.1 Reset" */
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while (timeout-- &&
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(tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
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udelay(100);
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}
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for (i = 0; i < init_length; i++)
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iowrite32(init_sequence[i], ioaddr + CSR12);
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ioread32(ioaddr + CSR12); /* flush posted writes */
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}
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tmp_info = get_u16(&misc_info[1]);
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if (tmp_info)
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tp->advertising[phy_num] = tmp_info | 1;
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@ -482,8 +482,11 @@ static inline void tulip_stop_rxtx(struct tulip_private *tp)
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udelay(10);
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if (!i)
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printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed\n",
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pci_name(tp->pdev));
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printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
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" (CSR5 0x%x CSR6 0x%x)\n",
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pci_name(tp->pdev),
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ioread32(ioaddr + CSR5),
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ioread32(ioaddr + CSR6));
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}
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}
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