ARM: OMAP2+: Remove omap4 pdata from hsmmc.c
This is no longer needed as omap4 is now booted using device tree. Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -29,7 +29,6 @@
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static u16 control_pbias_offset;
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static u16 control_devconf1_offset;
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static u16 control_mmc1;
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#define HSMMC_NAME_LEN 9
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@ -121,57 +120,6 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
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}
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}
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static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg;
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/*
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* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
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* card with Vcc regulator (from twl4030 or whatever). OMAP has both
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* 1.8V and 3.0V modes, controlled by the PBIAS register.
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*/
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reg = omap4_ctrl_pad_readl(control_pbias_offset);
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reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
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OMAP4_MMC1_PWRDNZ_MASK |
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OMAP4_MMC1_PBIASLITE_VMODE_MASK);
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omap4_ctrl_pad_writel(reg, control_pbias_offset);
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}
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static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg;
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unsigned long timeout;
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if (power_on) {
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reg = omap4_ctrl_pad_readl(control_pbias_offset);
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reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
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if ((1 << vdd) <= MMC_VDD_165_195)
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reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
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else
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reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
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reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
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OMAP4_MMC1_PWRDNZ_MASK);
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omap4_ctrl_pad_writel(reg, control_pbias_offset);
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timeout = jiffies + msecs_to_jiffies(5);
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do {
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reg = omap4_ctrl_pad_readl(control_pbias_offset);
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if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
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break;
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usleep_range(100, 200);
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} while (!time_after(jiffies, timeout));
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if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
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pr_err("Pbias Voltage is not same as LDO\n");
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/* Caution : On VMODE_ERROR Power Down MMC IO */
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reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
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omap4_ctrl_pad_writel(reg, control_pbias_offset);
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}
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}
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}
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static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
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{
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u32 reg;
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@ -317,11 +265,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
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mmc->slots[0].pm_caps = c->pm_caps;
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mmc->slots[0].internal_clock = !c->ext_clock;
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mmc->max_freq = c->max_freq;
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if (cpu_is_omap44xx())
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mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
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else
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mmc->reg_offset = 0;
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mmc->reg_offset = 0;
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mmc->get_context_loss_count = hsmmc_get_context_loss;
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mmc->slots[0].switch_pin = c->gpio_cd;
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@ -368,24 +312,14 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
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if (!soc_is_am35xx())
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mmc->slots[0].features |= HSMMC_HAS_PBIAS;
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if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
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mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
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switch (c->mmc) {
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case 1:
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if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
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/* on-chip level shifting via PBIAS0/PBIAS1 */
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if (cpu_is_omap44xx()) {
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mmc->slots[0].before_set_reg =
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omap4_hsmmc1_before_set_reg;
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mmc->slots[0].after_set_reg =
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omap4_hsmmc1_after_set_reg;
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} else {
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mmc->slots[0].before_set_reg =
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omap_hsmmc1_before_set_reg;
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mmc->slots[0].after_set_reg =
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omap_hsmmc1_after_set_reg;
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}
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mmc->slots[0].before_set_reg =
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omap_hsmmc1_before_set_reg;
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mmc->slots[0].after_set_reg =
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omap_hsmmc1_after_set_reg;
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}
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if (soc_is_am35xx())
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@ -563,34 +497,17 @@ free_mmc:
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void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
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{
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u32 reg;
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if (omap_hsmmc_done)
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return;
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omap_hsmmc_done = 1;
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if (!cpu_is_omap44xx()) {
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if (cpu_is_omap2430()) {
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control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
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control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
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} else {
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control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
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control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
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}
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if (cpu_is_omap2430()) {
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control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
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control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
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} else {
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control_pbias_offset =
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OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
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control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
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reg = omap4_ctrl_pad_readl(control_mmc1);
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reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
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OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
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reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
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OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
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reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
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OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
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OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
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omap4_ctrl_pad_writel(reg, control_mmc1);
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control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
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control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
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}
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for (; controllers->mmc; controllers++)
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