amd64_edac: Add support for F15h DCT PCI config accesses
F15h "multiplexes" between the configuration space of the two DRAM controllers by toggling D18F1x10C[DctCfgSel] while F10h has a different set of registers for DCT0, and DCT1 in extended PCI config space. Add DCT configuration space accessors per family thus wrapping all the different access prerequisites. Clean up code while at it, shorten names. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
parent
b6a280bb96
commit
b2b0c60543
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@ -107,6 +107,79 @@ struct scrubrate {
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{ 0x00, 0UL}, /* scrubbing off */
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};
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static int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
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u32 *val, const char *func)
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{
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int err = 0;
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err = pci_read_config_dword(pdev, offset, val);
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if (err)
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amd64_warn("%s: error reading F%dx%03x.\n",
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func, PCI_FUNC(pdev->devfn), offset);
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return err;
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}
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int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
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u32 val, const char *func)
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{
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int err = 0;
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err = pci_write_config_dword(pdev, offset, val);
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if (err)
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amd64_warn("%s: error writing to F%dx%03x.\n",
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func, PCI_FUNC(pdev->devfn), offset);
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return err;
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}
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/*
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*
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* Depending on the family, F2 DCT reads need special handling:
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*
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* K8: has a single DCT only
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*
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* F10h: each DCT has its own set of regs
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* DCT0 -> F2x040..
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* DCT1 -> F2x140..
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*
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* F15h: we select which DCT we access using F1x10C[DctCfgSel]
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*
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*/
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static int k8_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
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const char *func)
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{
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if (addr >= 0x100)
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return -EINVAL;
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return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
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}
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static int f10_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
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const char *func)
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{
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return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
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}
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static int f15_read_dct_pci_cfg(struct amd64_pvt *pvt, int addr, u32 *val,
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const char *func)
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{
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u32 reg = 0;
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u8 dct = 0;
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if (addr >= 0x140 && addr <= 0x1a0) {
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dct = 1;
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addr -= 0x100;
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}
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amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®);
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reg &= 0xfffffffe;
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reg |= dct;
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amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
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return __amd64_read_pci_cfg_dword(pvt->F2, addr, val, func);
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}
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/*
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* Memory scrubber control interface. For K8, memory scrubbing is handled by
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* hardware and can involve L2 cache, dcache as well as the main memory. With
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@ -824,7 +897,7 @@ static void amd64_dump_dramcfg_low(u32 dclr, int chan)
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}
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/* Display and decode various NB registers for debug purposes. */
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static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
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static void dump_misc_regs(struct amd64_pvt *pvt)
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{
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debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
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@ -864,13 +937,10 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
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amd64_dump_dramcfg_low(pvt->dclr1, 1);
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}
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/* Read in both of DBAM registers */
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static void amd64_read_dbam_reg(struct amd64_pvt *pvt)
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{
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amd64_read_pci_cfg(pvt->F2, DBAM0, &pvt->dbam0);
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if (boot_cpu_data.x86 >= 0x10)
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amd64_read_pci_cfg(pvt->F2, DBAM1, &pvt->dbam1);
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amd64_read_dct_pci_cfg(pvt, DBAM0, &pvt->dbam0);
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amd64_read_dct_pci_cfg(pvt, DBAM1, &pvt->dbam1);
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}
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/*
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@ -925,7 +995,7 @@ static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt)
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/*
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* Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers
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*/
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static void amd64_read_dct_base_mask(struct amd64_pvt *pvt)
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static void read_dct_base_mask(struct amd64_pvt *pvt)
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{
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int cs, reg;
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@ -933,37 +1003,33 @@ static void amd64_read_dct_base_mask(struct amd64_pvt *pvt)
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for (cs = 0; cs < pvt->cs_count; cs++) {
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reg = K8_DCSB0 + (cs * 4);
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if (!amd64_read_pci_cfg(pvt->F2, reg, &pvt->dcsb0[cs]))
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if (!amd64_read_dct_pci_cfg(pvt, reg, &pvt->dcsb0[cs]))
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debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n",
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cs, pvt->dcsb0[cs], reg);
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/* If DCT are NOT ganged, then read in DCT1's base */
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if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) {
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if (!dct_ganging_enabled(pvt)) {
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reg = F10_DCSB1 + (cs * 4);
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if (!amd64_read_pci_cfg(pvt->F2, reg,
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&pvt->dcsb1[cs]))
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if (!amd64_read_dct_pci_cfg(pvt, reg, &pvt->dcsb1[cs]))
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debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n",
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cs, pvt->dcsb1[cs], reg);
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} else {
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pvt->dcsb1[cs] = 0;
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}
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}
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for (cs = 0; cs < pvt->num_dcsm; cs++) {
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reg = K8_DCSM0 + (cs * 4);
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if (!amd64_read_pci_cfg(pvt->F2, reg, &pvt->dcsm0[cs]))
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if (!amd64_read_dct_pci_cfg(pvt, reg, &pvt->dcsm0[cs]))
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debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n",
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cs, pvt->dcsm0[cs], reg);
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/* If DCT are NOT ganged, then read in DCT1's mask */
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if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) {
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if (!dct_ganging_enabled(pvt)) {
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reg = F10_DCSM1 + (cs * 4);
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if (!amd64_read_pci_cfg(pvt->F2, reg,
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&pvt->dcsm1[cs]))
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if (!amd64_read_dct_pci_cfg(pvt, reg, &pvt->dcsm1[cs]))
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debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n",
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cs, pvt->dcsm1[cs], reg);
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} else {
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pvt->dcsm1[cs] = 0;
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}
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}
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}
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@ -999,7 +1065,7 @@ static int k8_early_channel_count(struct amd64_pvt *pvt)
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{
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int flag, err = 0;
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err = amd64_read_pci_cfg(pvt->F2, F10_DCLR_0, &pvt->dclr0);
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err = amd64_read_dct_pci_cfg(pvt, F10_DCLR_0, &pvt->dclr0);
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if (err)
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return err;
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@ -1163,7 +1229,7 @@ static int f10_early_channel_count(struct amd64_pvt *pvt)
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* both controllers since DIMMs can be placed in either one.
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*/
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for (i = 0; i < ARRAY_SIZE(dbams); i++) {
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if (amd64_read_pci_cfg(pvt->F2, dbams[i], &dbam))
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if (amd64_read_dct_pci_cfg(pvt, dbams[i], &dbam))
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goto err_reg;
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for (j = 0; j < 4; j++) {
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@ -1255,12 +1321,9 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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{
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if (!amd64_read_pci_cfg(pvt->F2, F10_DCTL_SEL_LOW,
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&pvt->dram_ctl_select_low)) {
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debugf0("F2x110 (DCTL Sel. Low): 0x%08x, "
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"High range addresses at: 0x%x\n",
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pvt->dram_ctl_select_low,
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dct_sel_baseaddr(pvt));
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if (!amd64_read_dct_pci_cfg(pvt, F10_DCTL_SEL_LOW, &pvt->dct_sel_low)) {
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debugf0("F2x110 (DCTL Sel. Low): 0x%08x, High range addrs at: 0x%x\n",
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pvt->dct_sel_low, dct_sel_baseaddr(pvt));
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debugf0(" DCT mode: %s, All DCTs on: %s\n",
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(dct_ganging_enabled(pvt) ? "ganged" : "unganged"),
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@ -1281,8 +1344,7 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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dct_sel_interleave_addr(pvt));
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}
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amd64_read_pci_cfg(pvt->F2, F10_DCTL_SEL_HIGH,
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&pvt->dram_ctl_select_high);
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amd64_read_dct_pci_cfg(pvt, F10_DCTL_SEL_HIGH, &pvt->dct_sel_hi);
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}
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/*
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@ -1292,7 +1354,7 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
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int hi_range_sel, u32 intlv_en)
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{
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u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1;
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u32 cs, temp, dct_sel_high = (pvt->dct_sel_low >> 1) & 1;
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if (dct_ganging_enabled(pvt))
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cs = 0;
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@ -1481,7 +1543,7 @@ static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range,
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*/
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hole_off = (pvt->dhar & 0x0000FF80);
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hole_valid = (pvt->dhar & 0x1);
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dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16;
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dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
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debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n",
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hole_off, hole_valid, intlv_sel);
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@ -1668,6 +1730,7 @@ static struct amd64_family_type amd64_family_types[] = {
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.read_dram_base_limit = k8_read_dram_base_limit,
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.map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow,
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.dbam_to_cs = k8_dbam_to_chip_select,
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.read_dct_pci_cfg = k8_read_dct_pci_cfg,
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}
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},
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[F10_CPUS] = {
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@ -1681,6 +1744,13 @@ static struct amd64_family_type amd64_family_types[] = {
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.read_dram_ctl_register = f10_read_dram_ctl_register,
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.map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow,
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.dbam_to_cs = f10_dbam_to_chip_select,
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.read_dct_pci_cfg = f10_read_dct_pci_cfg,
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}
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},
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[F15_CPUS] = {
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.ctl_name = "F15h",
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.ops = {
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.read_dct_pci_cfg = f15_read_dct_pci_cfg,
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}
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},
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};
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@ -2081,24 +2151,24 @@ static void read_mc_regs(struct amd64_pvt *pvt)
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}
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}
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amd64_read_dct_base_mask(pvt);
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read_dct_base_mask(pvt);
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amd64_read_pci_cfg(pvt->F1, K8_DHAR, &pvt->dhar);
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amd64_read_dbam_reg(pvt);
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amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
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amd64_read_pci_cfg(pvt->F2, F10_DCLR_0, &pvt->dclr0);
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amd64_read_pci_cfg(pvt->F2, F10_DCHR_0, &pvt->dchr0);
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amd64_read_dct_pci_cfg(pvt, F10_DCLR_0, &pvt->dclr0);
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amd64_read_dct_pci_cfg(pvt, F10_DCHR_0, &pvt->dchr0);
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if (boot_cpu_data.x86 >= 0x10) {
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if (!dct_ganging_enabled(pvt)) {
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amd64_read_pci_cfg(pvt->F2, F10_DCLR_1, &pvt->dclr1);
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amd64_read_pci_cfg(pvt->F2, F10_DCHR_1, &pvt->dchr1);
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}
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amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
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if (!dct_ganging_enabled(pvt)) {
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amd64_read_dct_pci_cfg(pvt, F10_DCLR_1, &pvt->dclr1);
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amd64_read_dct_pci_cfg(pvt, F10_DCHR_1, &pvt->dchr1);
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}
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if (boot_cpu_data.x86 >= 0x10)
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amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
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if (boot_cpu_data.x86 == 0x10 &&
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boot_cpu_data.x86_model > 7 &&
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/* F3x180[EccSymbolSize]=1 => x8 symbols */
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@ -2107,7 +2177,7 @@ static void read_mc_regs(struct amd64_pvt *pvt)
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else
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pvt->syn_type = 4;
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amd64_dump_misc_regs(pvt);
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dump_misc_regs(pvt);
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}
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/*
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@ -2342,7 +2412,7 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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s->nbctl_valid = true;
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value |= mask;
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pci_write_config_dword(F3, K8_NBCTL, value);
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amd64_write_pci_cfg(F3, K8_NBCTL, value);
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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@ -2357,7 +2427,7 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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/* Attempt to turn on DRAM ECC Enable */
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value |= K8_NBCFG_ECC_ENABLE;
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pci_write_config_dword(F3, K8_NBCFG, value);
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amd64_write_pci_cfg(F3, K8_NBCFG, value);
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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@ -2391,13 +2461,13 @@ static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid,
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value &= ~mask;
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value |= s->old_nbctl;
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pci_write_config_dword(F3, K8_NBCTL, value);
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amd64_write_pci_cfg(F3, K8_NBCTL, value);
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/* restore previous BIOS DRAM ECC "off" setting we force-enabled */
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if (!s->flags.nb_ecc_prev) {
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amd64_read_pci_cfg(F3, K8_NBCFG, &value);
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value &= ~K8_NBCFG_ECC_ENABLE;
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pci_write_config_dword(F3, K8_NBCFG, value);
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amd64_write_pci_cfg(F3, K8_NBCFG, value);
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}
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/* restore the NB Enable MCGCTL bit */
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@ -184,6 +184,7 @@
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/* NOTE: Extra mask bit vs K8 */
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#define f10_dhar_offset(dhar) ((dhar & F10_DHAR_OFFSET_MASK) << 16)
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#define DCT_CFG_SEL 0x10C
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/* F10 High BASE/LIMIT registers */
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#define F10_DRAM_BASE_HIGH 0x140
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@ -257,14 +258,14 @@
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#define F10_DCTL_SEL_LOW 0x110
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#define dct_sel_baseaddr(pvt) ((pvt->dram_ctl_select_low) & 0xFFFFF800)
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#define dct_sel_interleave_addr(pvt) (((pvt->dram_ctl_select_low) >> 6) & 0x3)
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#define dct_high_range_enabled(pvt) (pvt->dram_ctl_select_low & BIT(0))
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#define dct_interleave_enabled(pvt) (pvt->dram_ctl_select_low & BIT(2))
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#define dct_ganging_enabled(pvt) (pvt->dram_ctl_select_low & BIT(4))
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#define dct_data_intlv_enabled(pvt) (pvt->dram_ctl_select_low & BIT(5))
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#define dct_dram_enabled(pvt) (pvt->dram_ctl_select_low & BIT(8))
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#define dct_memory_cleared(pvt) (pvt->dram_ctl_select_low & BIT(10))
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#define dct_sel_baseaddr(pvt) ((pvt->dct_sel_low) & 0xFFFFF800)
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#define dct_sel_interleave_addr(pvt) (((pvt->dct_sel_low) >> 6) & 0x3)
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#define dct_high_range_enabled(pvt) (pvt->dct_sel_low & BIT(0))
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#define dct_interleave_enabled(pvt) (pvt->dct_sel_low & BIT(2))
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#define dct_ganging_enabled(pvt) (pvt->dct_sel_low & BIT(4))
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#define dct_data_intlv_enabled(pvt) (pvt->dct_sel_low & BIT(5))
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#define dct_dram_enabled(pvt) (pvt->dct_sel_low & BIT(8))
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#define dct_memory_cleared(pvt) (pvt->dct_sel_low & BIT(10))
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#define F10_DCTL_SEL_HIGH 0x114
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@ -380,9 +381,11 @@ static inline int get_node_id(struct pci_dev *pdev)
|
|||
return PCI_SLOT(pdev->devfn) - 0x18;
|
||||
}
|
||||
|
||||
enum amd64_chipset_families {
|
||||
enum amd_families {
|
||||
K8_CPUS = 0,
|
||||
F10_CPUS,
|
||||
F15_CPUS,
|
||||
NUM_FAMILIES,
|
||||
};
|
||||
|
||||
/* Error injection control structure */
|
||||
|
|
@ -448,9 +451,9 @@ struct amd64_pvt {
|
|||
u64 top_mem; /* top of memory below 4GB */
|
||||
u64 top_mem2; /* top of memory above 4GB */
|
||||
|
||||
u32 dram_ctl_select_low; /* DRAM Controller Select Low Reg */
|
||||
u32 dram_ctl_select_high; /* DRAM Controller Select High Reg */
|
||||
u32 online_spare; /* On-Line spare Reg */
|
||||
u32 dct_sel_low; /* DRAM Controller Select Low Reg */
|
||||
u32 dct_sel_hi; /* DRAM Controller Select High Reg */
|
||||
u32 online_spare; /* On-Line spare Reg */
|
||||
|
||||
/* x4 or x8 syndromes in use */
|
||||
u8 syn_type;
|
||||
|
|
@ -519,6 +522,8 @@ struct low_ops {
|
|||
void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci,
|
||||
struct err_regs *info, u64 SystemAddr);
|
||||
int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode);
|
||||
int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset,
|
||||
u32 *val, const char *func);
|
||||
};
|
||||
|
||||
struct amd64_family_type {
|
||||
|
|
@ -527,21 +532,17 @@ struct amd64_family_type {
|
|||
struct low_ops ops;
|
||||
};
|
||||
|
||||
static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
|
||||
u32 *val, const char *func)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
err = pci_read_config_dword(pdev, offset, val);
|
||||
if (err)
|
||||
amd64_warn("%s: error reading F%dx%x.\n",
|
||||
func, PCI_FUNC(pdev->devfn), offset);
|
||||
|
||||
return err;
|
||||
}
|
||||
int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
|
||||
u32 val, const char *func);
|
||||
|
||||
#define amd64_read_pci_cfg(pdev, offset, val) \
|
||||
amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
|
||||
__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
|
||||
|
||||
#define amd64_write_pci_cfg(pdev, offset, val) \
|
||||
__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
|
||||
|
||||
#define amd64_read_dct_pci_cfg(pvt, offset, val) \
|
||||
pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
|
||||
|
||||
/*
|
||||
* For future CPU versions, verify the following as new 'slow' rates appear and
|
||||
|
|
|
|||
|
|
@ -117,13 +117,13 @@ static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
|
|||
/* Form value to choose 16-byte section of cacheline */
|
||||
section = F10_NB_ARRAY_DRAM_ECC |
|
||||
SET_NB_ARRAY_ADDRESS(pvt->injection.section);
|
||||
pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
||||
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
||||
|
||||
word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
|
||||
pvt->injection.bit_map);
|
||||
|
||||
/* Issue 'word' and 'bit' along with the READ request */
|
||||
pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
||||
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
||||
|
||||
debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
|
||||
|
||||
|
|
@ -150,13 +150,13 @@ static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
|
|||
/* Form value to choose 16-byte section of cacheline */
|
||||
section = F10_NB_ARRAY_DRAM_ECC |
|
||||
SET_NB_ARRAY_ADDRESS(pvt->injection.section);
|
||||
pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
||||
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
||||
|
||||
word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
|
||||
pvt->injection.bit_map);
|
||||
|
||||
/* Issue 'word' and 'bit' along with the READ request */
|
||||
pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
||||
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
||||
|
||||
debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue