drm/amdgpu: Add helper to turn an existing VM into a compute VM
v2: Removed updating and checking of vm->vm_context v3: Enable amdgpu_vm_clear_bo in amdgpu_vm_make_compute Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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@ -2461,6 +2461,73 @@ error_free_sched_entity:
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return r;
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}
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/**
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* amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
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*
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* This only works on GFX VMs that don't have any BOs added and no
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* page tables allocated yet.
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*
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* Changes the following VM parameters:
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* - use_cpu_for_update
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* - pte_supports_ats
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* - pasid (old PASID is released, because compute manages its own PASIDs)
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*
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* Reinitializes the page directory to reflect the changed ATS
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* setting. May leave behind an unused shadow BO for the page
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* directory when switching from SDMA updates to CPU updates.
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*
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* Returns 0 for success, -errno for errors.
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*/
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int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
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{
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bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
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int r;
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r = amdgpu_bo_reserve(vm->root.base.bo, true);
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if (r)
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return r;
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/* Sanity checks */
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if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
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r = -EINVAL;
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goto error;
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}
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/* Check if PD needs to be reinitialized and do it before
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* changing any other state, in case it fails.
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*/
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if (pte_support_ats != vm->pte_support_ats) {
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r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
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adev->vm_manager.root_level,
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pte_support_ats);
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if (r)
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goto error;
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}
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/* Update VM state */
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vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
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AMDGPU_VM_USE_CPU_FOR_COMPUTE);
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vm->pte_support_ats = pte_support_ats;
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DRM_DEBUG_DRIVER("VM update mode is %s\n",
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vm->use_cpu_for_update ? "CPU" : "SDMA");
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WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
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"CPU update of VM recommended only for large BAR system\n");
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if (vm->pasid) {
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unsigned long flags;
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spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
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idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
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spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
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vm->pasid = 0;
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}
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error:
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amdgpu_bo_unreserve(vm->root.base.bo);
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return r;
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}
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/**
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* amdgpu_vm_free_levels - free PD/PT levels
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*
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@ -260,6 +260,7 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev);
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void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
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int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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int vm_context, unsigned int pasid);
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int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
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void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
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bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
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unsigned int pasid);
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