ALSA: hda - Add more register bits definitions
Added some missing register bits definitions to reduce magic numbers. Also renamed some to follow the names on the datasheet. Signed-off-by: Takashi Iwai <tiwai@suse.de>
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Takashi Iwai
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b05a7d4fed
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b21fadb9c1
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@ -138,14 +138,23 @@ MODULE_DESCRIPTION("Intel HDA driver");
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* registers
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*/
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#define ICH6_REG_GCAP 0x00
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#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
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#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
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#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
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#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
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#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
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#define ICH6_REG_VMIN 0x02
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#define ICH6_REG_VMAJ 0x03
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#define ICH6_REG_OUTPAY 0x04
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#define ICH6_REG_INPAY 0x06
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#define ICH6_REG_GCTL 0x08
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#define ICH6_GCTL_RESET (1 << 1) /* controller reset */
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#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
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#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
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#define ICH6_REG_WAKEEN 0x0c
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#define ICH6_REG_STATESTS 0x0e
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#define ICH6_REG_GSTS 0x10
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#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
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#define ICH6_REG_INTCTL 0x20
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#define ICH6_REG_INTSTS 0x24
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#define ICH6_REG_WALCLK 0x30
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@ -153,17 +162,27 @@ MODULE_DESCRIPTION("Intel HDA driver");
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#define ICH6_REG_CORBLBASE 0x40
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#define ICH6_REG_CORBUBASE 0x44
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#define ICH6_REG_CORBWP 0x48
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#define ICH6_REG_CORBRP 0x4A
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#define ICH6_REG_CORBRP 0x4a
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#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
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#define ICH6_REG_CORBCTL 0x4c
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#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
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#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
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#define ICH6_REG_CORBSTS 0x4d
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#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
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#define ICH6_REG_CORBSIZE 0x4e
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#define ICH6_REG_RIRBLBASE 0x50
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#define ICH6_REG_RIRBUBASE 0x54
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#define ICH6_REG_RIRBWP 0x58
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#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
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#define ICH6_REG_RINTCNT 0x5a
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#define ICH6_REG_RIRBCTL 0x5c
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#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
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#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
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#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
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#define ICH6_REG_RIRBSTS 0x5d
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#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
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#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
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#define ICH6_REG_RIRBSIZE 0x5e
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#define ICH6_REG_IC 0x60
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@ -260,16 +279,6 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
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#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
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#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
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/* GCTL unsolicited response enable bit */
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#define ICH6_GCTL_UREN (1<<8)
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/* GCTL reset bit */
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#define ICH6_GCTL_RESET (1<<0)
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/* CORB/RIRB control, read/write pointer */
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#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
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#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
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#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
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/* below are so far hardcoded - should read registers in future */
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#define ICH6_MAX_CORB_ENTRIES 256
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#define ICH6_MAX_RIRB_ENTRIES 256
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@ -515,9 +524,9 @@ static void azx_init_cmd_io(struct azx *chip)
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/* set the corb write pointer to 0 */
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azx_writew(chip, CORBWP, 0);
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/* reset the corb hw read pointer */
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azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
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azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
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/* enable corb dma */
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azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
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azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
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/* RIRB set up */
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chip->rirb.addr = chip->rb.addr + 2048;
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@ -529,7 +538,7 @@ static void azx_init_cmd_io(struct azx *chip)
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/* set the rirb size to 256 entries (ULI requires explicitly) */
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azx_writeb(chip, RIRBSIZE, 0x02);
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/* reset the rirb hw write pointer */
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azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
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azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
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/* set N=1, get RIRB response interrupt for new entry */
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azx_writew(chip, RINTCNT, 1);
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/* enable rirb dma and response irq */
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@ -796,7 +805,7 @@ static int azx_reset(struct azx *chip)
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}
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/* Accept unsolicited responses */
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
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/* detect codecs */
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if (!chip->codec_mask) {
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@ -2284,10 +2293,10 @@ static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
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/* ATI chips seems buggy about 64bit DMA addresses */
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if (chip->driver_type == AZX_DRIVER_ATI)
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gcap &= ~0x01;
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gcap &= ~ICH6_GCAP_64OK;
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/* allow 64bit DMA address if supported by H/W */
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if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
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if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
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pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
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else {
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pci_set_dma_mask(pci, DMA_BIT_MASK(32));
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