HSI: Introduce OMAP SSI driver
Add OMAP SSI driver to the HSI subsystem. The Synchronous Serial Interface (SSI) is a legacy version of HSI. As in the case of HSI, it is mainly used to connect Application engines (APE) with cellular modem engines (CMT) in cellular handsets. It provides a multichannel, full-duplex, multi-core communication with no reference clock. The OMAP SSI block is capable of reaching speeds of 110 Mbit/s. Signed-off-by: Carlos Chinea <carlos.chinea@nokia.com> Signed-off-by: Sebastian Reichel <sre@kernel.org> Tested-By: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
This commit is contained in:
Sebastian Reichel
parent
a2aa24734d
commit
b209e047bc
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@ -14,6 +14,7 @@ config HSI_BOARDINFO
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bool
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default y
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source "drivers/hsi/controllers/Kconfig"
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source "drivers/hsi/clients/Kconfig"
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endif # HSI
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@ -3,4 +3,5 @@
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#
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obj-$(CONFIG_HSI_BOARDINFO) += hsi_boardinfo.o
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obj-$(CONFIG_HSI) += hsi.o
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obj-y += controllers/
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obj-y += clients/
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@ -0,0 +1,19 @@
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#
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# HSI controllers configuration
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#
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comment "HSI controllers"
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config OMAP_SSI
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tristate "OMAP SSI hardware driver"
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depends on HSI && OF && (ARCH_OMAP3 || (ARM && COMPILE_TEST))
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---help---
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SSI is a legacy version of HSI. It is usually used to connect
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an application engine with a cellular modem.
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If you say Y here, you will enable the OMAP SSI hardware driver.
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If unsure, say N.
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config OMAP_SSI_PORT
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tristate
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default m if OMAP_SSI=m
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default y if OMAP_SSI=y
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@ -0,0 +1,6 @@
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#
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# Makefile for HSI controllers drivers
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#
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obj-$(CONFIG_OMAP_SSI) += omap_ssi.o
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obj-$(CONFIG_OMAP_SSI_PORT) += omap_ssi_port.o
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@ -0,0 +1,625 @@
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/* OMAP SSI driver.
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*
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* Copyright (C) 2010 Nokia Corporation. All rights reserved.
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* Copyright (C) 2014 Sebastian Reichel <sre@kernel.org>
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*
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* Contact: Carlos Chinea <carlos.chinea@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*/
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#include <linux/compiler.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/scatterlist.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/debugfs.h>
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#include <linux/pm_runtime.h>
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#include <linux/of_platform.h>
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#include <linux/hsi/hsi.h>
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#include <linux/idr.h>
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#include "omap_ssi_regs.h"
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#include "omap_ssi.h"
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/* For automatically allocated device IDs */
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static DEFINE_IDA(platform_omap_ssi_ida);
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#ifdef CONFIG_DEBUG_FS
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static int ssi_debug_show(struct seq_file *m, void *p __maybe_unused)
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{
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struct hsi_controller *ssi = m->private;
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struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
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void __iomem *sys = omap_ssi->sys;
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pm_runtime_get_sync(ssi->device.parent);
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seq_printf(m, "REVISION\t: 0x%08x\n", readl(sys + SSI_REVISION_REG));
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seq_printf(m, "SYSCONFIG\t: 0x%08x\n", readl(sys + SSI_SYSCONFIG_REG));
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seq_printf(m, "SYSSTATUS\t: 0x%08x\n", readl(sys + SSI_SYSSTATUS_REG));
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pm_runtime_put_sync(ssi->device.parent);
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return 0;
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}
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static int ssi_debug_gdd_show(struct seq_file *m, void *p __maybe_unused)
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{
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struct hsi_controller *ssi = m->private;
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struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
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void __iomem *gdd = omap_ssi->gdd;
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void __iomem *sys = omap_ssi->sys;
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int lch;
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pm_runtime_get_sync(ssi->device.parent);
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seq_printf(m, "GDD_MPU_STATUS\t: 0x%08x\n",
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readl(sys + SSI_GDD_MPU_IRQ_STATUS_REG));
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seq_printf(m, "GDD_MPU_ENABLE\t: 0x%08x\n\n",
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readl(sys + SSI_GDD_MPU_IRQ_ENABLE_REG));
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seq_printf(m, "HW_ID\t\t: 0x%08x\n",
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readl(gdd + SSI_GDD_HW_ID_REG));
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seq_printf(m, "PPORT_ID\t: 0x%08x\n",
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readl(gdd + SSI_GDD_PPORT_ID_REG));
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seq_printf(m, "MPORT_ID\t: 0x%08x\n",
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readl(gdd + SSI_GDD_MPORT_ID_REG));
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seq_printf(m, "TEST\t\t: 0x%08x\n",
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readl(gdd + SSI_GDD_TEST_REG));
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seq_printf(m, "GCR\t\t: 0x%08x\n",
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readl(gdd + SSI_GDD_GCR_REG));
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for (lch = 0; lch < SSI_MAX_GDD_LCH; lch++) {
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seq_printf(m, "\nGDD LCH %d\n=========\n", lch);
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seq_printf(m, "CSDP\t\t: 0x%04x\n",
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readw(gdd + SSI_GDD_CSDP_REG(lch)));
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seq_printf(m, "CCR\t\t: 0x%04x\n",
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readw(gdd + SSI_GDD_CCR_REG(lch)));
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seq_printf(m, "CICR\t\t: 0x%04x\n",
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readw(gdd + SSI_GDD_CICR_REG(lch)));
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seq_printf(m, "CSR\t\t: 0x%04x\n",
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readw(gdd + SSI_GDD_CSR_REG(lch)));
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seq_printf(m, "CSSA\t\t: 0x%08x\n",
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readl(gdd + SSI_GDD_CSSA_REG(lch)));
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seq_printf(m, "CDSA\t\t: 0x%08x\n",
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readl(gdd + SSI_GDD_CDSA_REG(lch)));
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seq_printf(m, "CEN\t\t: 0x%04x\n",
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readw(gdd + SSI_GDD_CEN_REG(lch)));
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seq_printf(m, "CSAC\t\t: 0x%04x\n",
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readw(gdd + SSI_GDD_CSAC_REG(lch)));
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seq_printf(m, "CDAC\t\t: 0x%04x\n",
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readw(gdd + SSI_GDD_CDAC_REG(lch)));
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seq_printf(m, "CLNK_CTRL\t: 0x%04x\n",
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readw(gdd + SSI_GDD_CLNK_CTRL_REG(lch)));
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}
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pm_runtime_put_sync(ssi->device.parent);
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return 0;
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}
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static int ssi_regs_open(struct inode *inode, struct file *file)
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{
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return single_open(file, ssi_debug_show, inode->i_private);
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}
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static int ssi_gdd_regs_open(struct inode *inode, struct file *file)
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{
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return single_open(file, ssi_debug_gdd_show, inode->i_private);
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}
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static const struct file_operations ssi_regs_fops = {
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.open = ssi_regs_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static const struct file_operations ssi_gdd_regs_fops = {
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.open = ssi_gdd_regs_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int __init ssi_debug_add_ctrl(struct hsi_controller *ssi)
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{
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struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
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struct dentry *dir;
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/* SSI controller */
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omap_ssi->dir = debugfs_create_dir(dev_name(&ssi->device), NULL);
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if (IS_ERR(omap_ssi->dir))
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return PTR_ERR(omap_ssi->dir);
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debugfs_create_file("regs", S_IRUGO, omap_ssi->dir, ssi,
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&ssi_regs_fops);
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/* SSI GDD (DMA) */
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dir = debugfs_create_dir("gdd", omap_ssi->dir);
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if (IS_ERR(dir))
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goto rback;
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debugfs_create_file("regs", S_IRUGO, dir, ssi, &ssi_gdd_regs_fops);
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return 0;
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rback:
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debugfs_remove_recursive(omap_ssi->dir);
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return PTR_ERR(dir);
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}
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static void ssi_debug_remove_ctrl(struct hsi_controller *ssi)
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{
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struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
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debugfs_remove_recursive(omap_ssi->dir);
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}
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#endif /* CONFIG_DEBUG_FS */
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/*
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* FIXME: Horrible HACK needed until we remove the useless wakeline test
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* in the CMT. To be removed !!!!
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*/
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void ssi_waketest(struct hsi_client *cl, unsigned int enable)
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{
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struct hsi_port *port = hsi_get_port(cl);
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struct omap_ssi_port *omap_port = hsi_port_drvdata(port);
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struct hsi_controller *ssi = to_hsi_controller(port->device.parent);
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struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
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omap_port->wktest = !!enable;
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if (omap_port->wktest) {
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pm_runtime_get_sync(ssi->device.parent);
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writel_relaxed(SSI_WAKE(0),
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omap_ssi->sys + SSI_SET_WAKE_REG(port->num));
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} else {
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writel_relaxed(SSI_WAKE(0),
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omap_ssi->sys + SSI_CLEAR_WAKE_REG(port->num));
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pm_runtime_put_sync(ssi->device.parent);
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}
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}
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EXPORT_SYMBOL_GPL(ssi_waketest);
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static void ssi_gdd_complete(struct hsi_controller *ssi, unsigned int lch)
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{
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struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
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struct hsi_msg *msg = omap_ssi->gdd_trn[lch].msg;
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struct hsi_port *port = to_hsi_port(msg->cl->device.parent);
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struct omap_ssi_port *omap_port = hsi_port_drvdata(port);
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unsigned int dir;
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u32 csr;
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u32 val;
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spin_lock(&omap_ssi->lock);
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val = readl(omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
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val &= ~SSI_GDD_LCH(lch);
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writel_relaxed(val, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
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if (msg->ttype == HSI_MSG_READ) {
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dir = DMA_FROM_DEVICE;
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val = SSI_DATAAVAILABLE(msg->channel);
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pm_runtime_put_sync(ssi->device.parent);
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} else {
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dir = DMA_TO_DEVICE;
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val = SSI_DATAACCEPT(msg->channel);
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/* Keep clocks reference for write pio event */
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}
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dma_unmap_sg(&ssi->device, msg->sgt.sgl, msg->sgt.nents, dir);
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csr = readw(omap_ssi->gdd + SSI_GDD_CSR_REG(lch));
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omap_ssi->gdd_trn[lch].msg = NULL; /* release GDD lch */
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dev_dbg(&port->device, "DMA completed ch %d ttype %d\n",
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msg->channel, msg->ttype);
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spin_unlock(&omap_ssi->lock);
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if (csr & SSI_CSR_TOUR) { /* Timeout error */
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msg->status = HSI_STATUS_ERROR;
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msg->actual_len = 0;
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spin_lock(&omap_port->lock);
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list_del(&msg->link); /* Dequeue msg */
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spin_unlock(&omap_port->lock);
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msg->complete(msg);
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return;
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}
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spin_lock(&omap_port->lock);
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val |= readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
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writel_relaxed(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
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spin_unlock(&omap_port->lock);
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msg->status = HSI_STATUS_COMPLETED;
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msg->actual_len = sg_dma_len(msg->sgt.sgl);
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}
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static void ssi_gdd_tasklet(unsigned long dev)
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{
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struct hsi_controller *ssi = (struct hsi_controller *)dev;
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struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
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void __iomem *sys = omap_ssi->sys;
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unsigned int lch;
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u32 status_reg;
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pm_runtime_get_sync(ssi->device.parent);
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status_reg = readl(sys + SSI_GDD_MPU_IRQ_STATUS_REG);
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for (lch = 0; lch < SSI_MAX_GDD_LCH; lch++) {
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if (status_reg & SSI_GDD_LCH(lch))
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ssi_gdd_complete(ssi, lch);
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}
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writel_relaxed(status_reg, sys + SSI_GDD_MPU_IRQ_STATUS_REG);
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status_reg = readl(sys + SSI_GDD_MPU_IRQ_STATUS_REG);
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pm_runtime_put_sync(ssi->device.parent);
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if (status_reg)
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tasklet_hi_schedule(&omap_ssi->gdd_tasklet);
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else
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enable_irq(omap_ssi->gdd_irq);
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}
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static irqreturn_t ssi_gdd_isr(int irq, void *ssi)
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{
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struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
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tasklet_hi_schedule(&omap_ssi->gdd_tasklet);
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disable_irq_nosync(irq);
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return IRQ_HANDLED;
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}
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static unsigned long ssi_get_clk_rate(struct hsi_controller *ssi)
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{
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struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
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unsigned long rate = clk_get_rate(omap_ssi->fck);
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return rate;
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}
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static int __init ssi_get_iomem(struct platform_device *pd,
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const char *name, void __iomem **pbase, dma_addr_t *phy)
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{
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struct resource *mem;
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struct resource *ioarea;
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void __iomem *base;
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struct hsi_controller *ssi = platform_get_drvdata(pd);
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mem = platform_get_resource_byname(pd, IORESOURCE_MEM, name);
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if (!mem) {
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dev_err(&pd->dev, "IO memory region missing (%s)\n", name);
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return -ENXIO;
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}
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ioarea = devm_request_mem_region(&ssi->device, mem->start,
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resource_size(mem), dev_name(&pd->dev));
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if (!ioarea) {
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dev_err(&pd->dev, "%s IO memory region request failed\n",
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mem->name);
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return -ENXIO;
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}
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base = devm_ioremap(&ssi->device, mem->start, resource_size(mem));
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if (!base) {
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dev_err(&pd->dev, "%s IO remap failed\n", mem->name);
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return -ENXIO;
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}
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*pbase = base;
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if (phy)
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*phy = mem->start;
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return 0;
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}
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static int __init ssi_add_controller(struct hsi_controller *ssi,
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struct platform_device *pd)
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{
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struct omap_ssi_controller *omap_ssi;
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int err;
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omap_ssi = devm_kzalloc(&ssi->device, sizeof(*omap_ssi), GFP_KERNEL);
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if (!omap_ssi) {
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dev_err(&pd->dev, "not enough memory for omap ssi\n");
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return -ENOMEM;
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}
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ssi->id = ida_simple_get(&platform_omap_ssi_ida, 0, 0, GFP_KERNEL);
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if (ssi->id < 0) {
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err = ssi->id;
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goto out_err;
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}
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ssi->owner = THIS_MODULE;
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ssi->device.parent = &pd->dev;
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dev_set_name(&ssi->device, "ssi%d", ssi->id);
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hsi_controller_set_drvdata(ssi, omap_ssi);
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omap_ssi->dev = &ssi->device;
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err = ssi_get_iomem(pd, "sys", &omap_ssi->sys, NULL);
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if (err < 0)
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goto out_err;
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err = ssi_get_iomem(pd, "gdd", &omap_ssi->gdd, NULL);
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if (err < 0)
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goto out_err;
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omap_ssi->gdd_irq = platform_get_irq_byname(pd, "gdd_mpu");
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if (omap_ssi->gdd_irq < 0) {
|
||||
dev_err(&pd->dev, "GDD IRQ resource missing\n");
|
||||
err = omap_ssi->gdd_irq;
|
||||
goto out_err;
|
||||
}
|
||||
tasklet_init(&omap_ssi->gdd_tasklet, ssi_gdd_tasklet,
|
||||
(unsigned long)ssi);
|
||||
err = devm_request_irq(&ssi->device, omap_ssi->gdd_irq, ssi_gdd_isr,
|
||||
0, "gdd_mpu", ssi);
|
||||
if (err < 0) {
|
||||
dev_err(&ssi->device, "Request GDD IRQ %d failed (%d)",
|
||||
omap_ssi->gdd_irq, err);
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
omap_ssi->port = devm_kzalloc(&ssi->device,
|
||||
sizeof(struct omap_ssi_port *) * ssi->num_ports, GFP_KERNEL);
|
||||
if (!omap_ssi->port) {
|
||||
err = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
omap_ssi->fck = devm_clk_get(&ssi->device, "ssi_ssr_fck");
|
||||
if (IS_ERR(omap_ssi->fck)) {
|
||||
dev_err(&pd->dev, "Could not acquire clock \"ssi_ssr_fck\": %li\n",
|
||||
PTR_ERR(omap_ssi->fck));
|
||||
err = -ENODEV;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
/* TODO: find register, which can be used to detect context loss */
|
||||
omap_ssi->get_loss = NULL;
|
||||
|
||||
omap_ssi->max_speed = UINT_MAX;
|
||||
spin_lock_init(&omap_ssi->lock);
|
||||
err = hsi_register_controller(ssi);
|
||||
|
||||
if (err < 0)
|
||||
goto out_err;
|
||||
|
||||
return 0;
|
||||
|
||||
out_err:
|
||||
ida_simple_remove(&platform_omap_ssi_ida, ssi->id);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __init ssi_hw_init(struct hsi_controller *ssi)
|
||||
{
|
||||
struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
|
||||
unsigned int i;
|
||||
u32 val;
|
||||
int err;
|
||||
|
||||
err = pm_runtime_get_sync(ssi->device.parent);
|
||||
if (err < 0) {
|
||||
dev_err(&ssi->device, "runtime PM failed %d\n", err);
|
||||
return err;
|
||||
}
|
||||
/* Reseting SSI controller */
|
||||
writel_relaxed(SSI_SOFTRESET, omap_ssi->sys + SSI_SYSCONFIG_REG);
|
||||
val = readl(omap_ssi->sys + SSI_SYSSTATUS_REG);
|
||||
for (i = 0; ((i < 20) && !(val & SSI_RESETDONE)); i++) {
|
||||
msleep(20);
|
||||
val = readl(omap_ssi->sys + SSI_SYSSTATUS_REG);
|
||||
}
|
||||
if (!(val & SSI_RESETDONE)) {
|
||||
dev_err(&ssi->device, "SSI HW reset failed\n");
|
||||
pm_runtime_put_sync(ssi->device.parent);
|
||||
return -EIO;
|
||||
}
|
||||
/* Reseting GDD */
|
||||
writel_relaxed(SSI_SWRESET, omap_ssi->gdd + SSI_GDD_GRST_REG);
|
||||
/* Get FCK rate in KHz */
|
||||
omap_ssi->fck_rate = DIV_ROUND_CLOSEST(ssi_get_clk_rate(ssi), 1000);
|
||||
dev_dbg(&ssi->device, "SSI fck rate %lu KHz\n", omap_ssi->fck_rate);
|
||||
/* Set default PM settings */
|
||||
val = SSI_AUTOIDLE | SSI_SIDLEMODE_SMART | SSI_MIDLEMODE_SMART;
|
||||
writel_relaxed(val, omap_ssi->sys + SSI_SYSCONFIG_REG);
|
||||
omap_ssi->sysconfig = val;
|
||||
writel_relaxed(SSI_CLK_AUTOGATING_ON, omap_ssi->sys + SSI_GDD_GCR_REG);
|
||||
omap_ssi->gdd_gcr = SSI_CLK_AUTOGATING_ON;
|
||||
pm_runtime_put_sync(ssi->device.parent);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ssi_remove_controller(struct hsi_controller *ssi)
|
||||
{
|
||||
struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
|
||||
int id = ssi->id;
|
||||
tasklet_kill(&omap_ssi->gdd_tasklet);
|
||||
hsi_unregister_controller(ssi);
|
||||
ida_simple_remove(&platform_omap_ssi_ida, id);
|
||||
}
|
||||
|
||||
static inline int ssi_of_get_available_ports_count(const struct device_node *np)
|
||||
{
|
||||
struct device_node *child;
|
||||
int num = 0;
|
||||
|
||||
for_each_available_child_of_node(np, child)
|
||||
if (of_device_is_compatible(child, "ti,omap3-ssi-port"))
|
||||
num++;
|
||||
|
||||
return num;
|
||||
}
|
||||
|
||||
static int ssi_remove_ports(struct device *dev, void *c)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(dev);
|
||||
|
||||
of_device_unregister(pdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init ssi_probe(struct platform_device *pd)
|
||||
{
|
||||
struct platform_device *childpdev;
|
||||
struct device_node *np = pd->dev.of_node;
|
||||
struct device_node *child;
|
||||
struct hsi_controller *ssi;
|
||||
int err;
|
||||
int num_ports;
|
||||
|
||||
if (!np) {
|
||||
dev_err(&pd->dev, "missing device tree data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
num_ports = ssi_of_get_available_ports_count(np);
|
||||
|
||||
ssi = hsi_alloc_controller(num_ports, GFP_KERNEL);
|
||||
if (!ssi) {
|
||||
dev_err(&pd->dev, "No memory for controller\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pd, ssi);
|
||||
|
||||
err = ssi_add_controller(ssi, pd);
|
||||
if (err < 0)
|
||||
goto out1;
|
||||
|
||||
pm_runtime_irq_safe(&pd->dev);
|
||||
pm_runtime_enable(&pd->dev);
|
||||
|
||||
err = ssi_hw_init(ssi);
|
||||
if (err < 0)
|
||||
goto out2;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
err = ssi_debug_add_ctrl(ssi);
|
||||
if (err < 0)
|
||||
goto out2;
|
||||
#endif
|
||||
|
||||
for_each_available_child_of_node(np, child) {
|
||||
if (!of_device_is_compatible(child, "ti,omap3-ssi-port"))
|
||||
continue;
|
||||
|
||||
childpdev = of_platform_device_create(child, NULL, &pd->dev);
|
||||
if (!childpdev) {
|
||||
err = -ENODEV;
|
||||
dev_err(&pd->dev, "failed to create ssi controller port\n");
|
||||
goto out3;
|
||||
}
|
||||
}
|
||||
|
||||
dev_info(&pd->dev, "ssi controller %d initialized (%d ports)!\n",
|
||||
ssi->id, num_ports);
|
||||
return err;
|
||||
out3:
|
||||
device_for_each_child(&pd->dev, NULL, ssi_remove_ports);
|
||||
out2:
|
||||
ssi_remove_controller(ssi);
|
||||
out1:
|
||||
platform_set_drvdata(pd, NULL);
|
||||
pm_runtime_disable(&pd->dev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __exit ssi_remove(struct platform_device *pd)
|
||||
{
|
||||
struct hsi_controller *ssi = platform_get_drvdata(pd);
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
ssi_debug_remove_ctrl(ssi);
|
||||
#endif
|
||||
ssi_remove_controller(ssi);
|
||||
platform_set_drvdata(pd, NULL);
|
||||
|
||||
pm_runtime_disable(&pd->dev);
|
||||
|
||||
/* cleanup of of_platform_populate() call */
|
||||
device_for_each_child(&pd->dev, NULL, ssi_remove_ports);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_RUNTIME
|
||||
static int omap_ssi_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct hsi_controller *ssi = dev_get_drvdata(dev);
|
||||
struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
|
||||
|
||||
dev_dbg(dev, "runtime suspend!\n");
|
||||
|
||||
if (omap_ssi->get_loss)
|
||||
omap_ssi->loss_count =
|
||||
omap_ssi->get_loss(ssi->device.parent);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap_ssi_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct hsi_controller *ssi = dev_get_drvdata(dev);
|
||||
struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
|
||||
|
||||
dev_dbg(dev, "runtime resume!\n");
|
||||
|
||||
if ((omap_ssi->get_loss) && (omap_ssi->loss_count ==
|
||||
omap_ssi->get_loss(ssi->device.parent)))
|
||||
return 0;
|
||||
|
||||
writel_relaxed(omap_ssi->gdd_gcr, omap_ssi->gdd + SSI_GDD_GCR_REG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops omap_ssi_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(omap_ssi_runtime_suspend, omap_ssi_runtime_resume,
|
||||
NULL)
|
||||
};
|
||||
|
||||
#define DEV_PM_OPS (&omap_ssi_pm_ops)
|
||||
#else
|
||||
#define DEV_PM_OPS NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id omap_ssi_of_match[] = {
|
||||
{ .compatible = "ti,omap3-ssi", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, omap_ssi_of_match);
|
||||
#else
|
||||
#define omap_ssi_of_match NULL
|
||||
#endif
|
||||
|
||||
static struct platform_driver ssi_pdriver = {
|
||||
.remove = __exit_p(ssi_remove),
|
||||
.driver = {
|
||||
.name = "omap_ssi",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = DEV_PM_OPS,
|
||||
.of_match_table = omap_ssi_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver_probe(ssi_pdriver, ssi_probe);
|
||||
|
||||
MODULE_ALIAS("platform:omap_ssi");
|
||||
MODULE_AUTHOR("Carlos Chinea <carlos.chinea@nokia.com>");
|
||||
MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>");
|
||||
MODULE_DESCRIPTION("Synchronous Serial Interface Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
/* OMAP SSI internal interface.
|
||||
*
|
||||
* Copyright (C) 2010 Nokia Corporation. All rights reserved.
|
||||
* Copyright (C) 2013 Sebastian Reichel
|
||||
*
|
||||
* Contact: Carlos Chinea <carlos.chinea@nokia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_HSI_OMAP_SSI_H__
|
||||
#define __LINUX_HSI_OMAP_SSI_H__
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/hsi/hsi.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#define SSI_MAX_CHANNELS 8
|
||||
#define SSI_MAX_GDD_LCH 8
|
||||
#define SSI_BYTES_TO_FRAMES(x) ((((x) - 1) >> 2) + 1)
|
||||
|
||||
/**
|
||||
* struct omap_ssm_ctx - OMAP synchronous serial module (TX/RX) context
|
||||
* @mode: Bit transmission mode
|
||||
* @channels: Number of channels
|
||||
* @framesize: Frame size in bits
|
||||
* @timeout: RX frame timeout
|
||||
* @divisor: TX divider
|
||||
* @arb_mode: Arbitration mode for TX frame (Round robin, priority)
|
||||
*/
|
||||
struct omap_ssm_ctx {
|
||||
u32 mode;
|
||||
u32 channels;
|
||||
u32 frame_size;
|
||||
union {
|
||||
u32 timeout; /* Rx Only */
|
||||
struct {
|
||||
u32 arb_mode;
|
||||
u32 divisor;
|
||||
}; /* Tx only */
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_ssi_port - OMAP SSI port data
|
||||
* @dev: device associated to the port (HSI port)
|
||||
* @pdev: platform device associated to the port
|
||||
* @sst_dma: SSI transmitter physical base address
|
||||
* @ssr_dma: SSI receiver physical base address
|
||||
* @sst_base: SSI transmitter base address
|
||||
* @ssr_base: SSI receiver base address
|
||||
* @wk_lock: spin lock to serialize access to the wake lines
|
||||
* @lock: Spin lock to serialize access to the SSI port
|
||||
* @channels: Current number of channels configured (1,2,4 or 8)
|
||||
* @txqueue: TX message queues
|
||||
* @rxqueue: RX message queues
|
||||
* @brkqueue: Queue of incoming HWBREAK requests (FRAME mode)
|
||||
* @irq: IRQ number
|
||||
* @wake_irq: IRQ number for incoming wake line (-1 if none)
|
||||
* @wake_gpio: GPIO number for incoming wake line (-1 if none)
|
||||
* @pio_tasklet: Bottom half for PIO transfers and events
|
||||
* @wake_tasklet: Bottom half for incoming wake events
|
||||
* @wkin_cken: Keep track of clock references due to the incoming wake line
|
||||
* @wk_refcount: Reference count for output wake line
|
||||
* @sys_mpu_enable: Context for the interrupt enable register for irq 0
|
||||
* @sst: Context for the synchronous serial transmitter
|
||||
* @ssr: Context for the synchronous serial receiver
|
||||
*/
|
||||
struct omap_ssi_port {
|
||||
struct device *dev;
|
||||
struct device *pdev;
|
||||
dma_addr_t sst_dma;
|
||||
dma_addr_t ssr_dma;
|
||||
void __iomem *sst_base;
|
||||
void __iomem *ssr_base;
|
||||
spinlock_t wk_lock;
|
||||
spinlock_t lock;
|
||||
unsigned int channels;
|
||||
struct list_head txqueue[SSI_MAX_CHANNELS];
|
||||
struct list_head rxqueue[SSI_MAX_CHANNELS];
|
||||
struct list_head brkqueue;
|
||||
unsigned int irq;
|
||||
int wake_irq;
|
||||
int wake_gpio;
|
||||
struct tasklet_struct pio_tasklet;
|
||||
struct tasklet_struct wake_tasklet;
|
||||
bool wktest:1; /* FIXME: HACK to be removed */
|
||||
bool wkin_cken:1; /* Workaround */
|
||||
unsigned int wk_refcount;
|
||||
/* OMAP SSI port context */
|
||||
u32 sys_mpu_enable; /* We use only one irq */
|
||||
struct omap_ssm_ctx sst;
|
||||
struct omap_ssm_ctx ssr;
|
||||
u32 loss_count;
|
||||
u32 port_id;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *dir;
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* struct gdd_trn - GDD transaction data
|
||||
* @msg: Pointer to the HSI message being served
|
||||
* @sg: Pointer to the current sg entry being served
|
||||
*/
|
||||
struct gdd_trn {
|
||||
struct hsi_msg *msg;
|
||||
struct scatterlist *sg;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_ssi_controller - OMAP SSI controller data
|
||||
* @dev: device associated to the controller (HSI controller)
|
||||
* @sys: SSI I/O base address
|
||||
* @gdd: GDD I/O base address
|
||||
* @fck: SSI functional clock
|
||||
* @gdd_irq: IRQ line for GDD
|
||||
* @gdd_tasklet: bottom half for DMA transfers
|
||||
* @gdd_trn: Array of GDD transaction data for ongoing GDD transfers
|
||||
* @lock: lock to serialize access to GDD
|
||||
* @loss_count: To follow if we need to restore context or not
|
||||
* @max_speed: Maximum TX speed (Kb/s) set by the clients.
|
||||
* @sysconfig: SSI controller saved context
|
||||
* @gdd_gcr: SSI GDD saved context
|
||||
* @get_loss: Pointer to omap_pm_get_dev_context_loss_count, if any
|
||||
* @port: Array of pointers of the ports of the controller
|
||||
* @dir: Debugfs SSI root directory
|
||||
*/
|
||||
struct omap_ssi_controller {
|
||||
struct device *dev;
|
||||
void __iomem *sys;
|
||||
void __iomem *gdd;
|
||||
struct clk *fck;
|
||||
unsigned int gdd_irq;
|
||||
struct tasklet_struct gdd_tasklet;
|
||||
struct gdd_trn gdd_trn[SSI_MAX_GDD_LCH];
|
||||
spinlock_t lock;
|
||||
unsigned long fck_rate;
|
||||
u32 loss_count;
|
||||
u32 max_speed;
|
||||
/* OMAP SSI Controller context */
|
||||
u32 sysconfig;
|
||||
u32 gdd_gcr;
|
||||
int (*get_loss)(struct device *dev);
|
||||
struct omap_ssi_port **port;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *dir;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* __LINUX_HSI_OMAP_SSI_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,171 @@
|
|||
/* Hardware definitions for SSI.
|
||||
*
|
||||
* Copyright (C) 2010 Nokia Corporation. All rights reserved.
|
||||
*
|
||||
* Contact: Carlos Chinea <carlos.chinea@nokia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __OMAP_SSI_REGS_H__
|
||||
#define __OMAP_SSI_REGS_H__
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/*
|
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* SSI SYS registers
|
||||
*/
|
||||
#define SSI_REVISION_REG 0
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# define SSI_REV_MAJOR 0xf0
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# define SSI_REV_MINOR 0xf
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#define SSI_SYSCONFIG_REG 0x10
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# define SSI_AUTOIDLE (1 << 0)
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# define SSI_SOFTRESET (1 << 1)
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# define SSI_SIDLEMODE_FORCE 0
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# define SSI_SIDLEMODE_NO (1 << 3)
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# define SSI_SIDLEMODE_SMART (1 << 4)
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# define SSI_SIDLEMODE_MASK 0x18
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# define SSI_MIDLEMODE_FORCE 0
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# define SSI_MIDLEMODE_NO (1 << 12)
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# define SSI_MIDLEMODE_SMART (1 << 13)
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# define SSI_MIDLEMODE_MASK 0x3000
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#define SSI_SYSSTATUS_REG 0x14
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# define SSI_RESETDONE 1
|
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#define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2))
|
||||
#define SSI_MPU_ENABLE_REG(port, irq) (0x80c + ((port) * 0x10) + ((irq) * 8))
|
||||
# define SSI_DATAACCEPT(channel) (1 << (channel))
|
||||
# define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8))
|
||||
# define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16))
|
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# define SSI_ERROROCCURED (1 << 24)
|
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# define SSI_BREAKDETECTED (1 << 25)
|
||||
#define SSI_GDD_MPU_IRQ_STATUS_REG 0x0800
|
||||
#define SSI_GDD_MPU_IRQ_ENABLE_REG 0x0804
|
||||
# define SSI_GDD_LCH(channel) (1 << (channel))
|
||||
#define SSI_WAKE_REG(port) (0xc00 + ((port) * 0x10))
|
||||
#define SSI_CLEAR_WAKE_REG(port) (0xc04 + ((port) * 0x10))
|
||||
#define SSI_SET_WAKE_REG(port) (0xc08 + ((port) * 0x10))
|
||||
# define SSI_WAKE(channel) (1 << (channel))
|
||||
# define SSI_WAKE_MASK 0xff
|
||||
|
||||
/*
|
||||
* SSI SST registers
|
||||
*/
|
||||
#define SSI_SST_ID_REG 0
|
||||
#define SSI_SST_MODE_REG 4
|
||||
# define SSI_MODE_VAL_MASK 3
|
||||
# define SSI_MODE_SLEEP 0
|
||||
# define SSI_MODE_STREAM 1
|
||||
# define SSI_MODE_FRAME 2
|
||||
# define SSI_MODE_MULTIPOINTS 3
|
||||
#define SSI_SST_FRAMESIZE_REG 8
|
||||
# define SSI_FRAMESIZE_DEFAULT 31
|
||||
#define SSI_SST_TXSTATE_REG 0xc
|
||||
# define SSI_TXSTATE_IDLE 0
|
||||
#define SSI_SST_BUFSTATE_REG 0x10
|
||||
# define SSI_FULL(channel) (1 << (channel))
|
||||
#define SSI_SST_DIVISOR_REG 0x18
|
||||
# define SSI_MAX_DIVISOR 127
|
||||
#define SSI_SST_BREAK_REG 0x20
|
||||
#define SSI_SST_CHANNELS_REG 0x24
|
||||
# define SSI_CHANNELS_DEFAULT 4
|
||||
#define SSI_SST_ARBMODE_REG 0x28
|
||||
# define SSI_ARBMODE_ROUNDROBIN 0
|
||||
# define SSI_ARBMODE_PRIORITY 1
|
||||
#define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4))
|
||||
#define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4))
|
||||
|
||||
/*
|
||||
* SSI SSR registers
|
||||
*/
|
||||
#define SSI_SSR_ID_REG 0
|
||||
#define SSI_SSR_MODE_REG 4
|
||||
#define SSI_SSR_FRAMESIZE_REG 8
|
||||
#define SSI_SSR_RXSTATE_REG 0xc
|
||||
#define SSI_SSR_BUFSTATE_REG 0x10
|
||||
# define SSI_NOTEMPTY(channel) (1 << (channel))
|
||||
#define SSI_SSR_BREAK_REG 0x1c
|
||||
#define SSI_SSR_ERROR_REG 0x20
|
||||
#define SSI_SSR_ERRORACK_REG 0x24
|
||||
#define SSI_SSR_OVERRUN_REG 0x2c
|
||||
#define SSI_SSR_OVERRUNACK_REG 0x30
|
||||
#define SSI_SSR_TIMEOUT_REG 0x34
|
||||
# define SSI_TIMEOUT_DEFAULT 0
|
||||
#define SSI_SSR_CHANNELS_REG 0x28
|
||||
#define SSI_SSR_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4))
|
||||
#define SSI_SSR_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4))
|
||||
|
||||
/*
|
||||
* SSI GDD registers
|
||||
*/
|
||||
#define SSI_GDD_HW_ID_REG 0
|
||||
#define SSI_GDD_PPORT_ID_REG 0x10
|
||||
#define SSI_GDD_MPORT_ID_REG 0x14
|
||||
#define SSI_GDD_PPORT_SR_REG 0x20
|
||||
#define SSI_GDD_MPORT_SR_REG 0x24
|
||||
# define SSI_ACTIVE_LCH_NUM_MASK 0xff
|
||||
#define SSI_GDD_TEST_REG 0x40
|
||||
# define SSI_TEST 1
|
||||
#define SSI_GDD_GCR_REG 0x100
|
||||
# define SSI_CLK_AUTOGATING_ON (1 << 3)
|
||||
# define SSI_FREE (1 << 2)
|
||||
# define SSI_SWITCH_OFF (1 << 0)
|
||||
#define SSI_GDD_GRST_REG 0x200
|
||||
# define SSI_SWRESET 1
|
||||
#define SSI_GDD_CSDP_REG(channel) (0x800 + ((channel) * 0x40))
|
||||
# define SSI_DST_BURST_EN_MASK 0xc000
|
||||
# define SSI_DST_SINGLE_ACCESS0 0
|
||||
# define SSI_DST_SINGLE_ACCESS (1 << 14)
|
||||
# define SSI_DST_BURST_4x32_BIT (2 << 14)
|
||||
# define SSI_DST_BURST_8x32_BIT (3 << 14)
|
||||
# define SSI_DST_MASK 0x1e00
|
||||
# define SSI_DST_MEMORY_PORT (8 << 9)
|
||||
# define SSI_DST_PERIPHERAL_PORT (9 << 9)
|
||||
# define SSI_SRC_BURST_EN_MASK 0x180
|
||||
# define SSI_SRC_SINGLE_ACCESS0 0
|
||||
# define SSI_SRC_SINGLE_ACCESS (1 << 7)
|
||||
# define SSI_SRC_BURST_4x32_BIT (2 << 7)
|
||||
# define SSI_SRC_BURST_8x32_BIT (3 << 7)
|
||||
# define SSI_SRC_MASK 0x3c
|
||||
# define SSI_SRC_MEMORY_PORT (8 << 2)
|
||||
# define SSI_SRC_PERIPHERAL_PORT (9 << 2)
|
||||
# define SSI_DATA_TYPE_MASK 3
|
||||
# define SSI_DATA_TYPE_S32 2
|
||||
#define SSI_GDD_CCR_REG(channel) (0x802 + ((channel) * 0x40))
|
||||
# define SSI_DST_AMODE_MASK (3 << 14)
|
||||
# define SSI_DST_AMODE_CONST 0
|
||||
# define SSI_DST_AMODE_POSTINC (1 << 12)
|
||||
# define SSI_SRC_AMODE_MASK (3 << 12)
|
||||
# define SSI_SRC_AMODE_CONST 0
|
||||
# define SSI_SRC_AMODE_POSTINC (1 << 12)
|
||||
# define SSI_CCR_ENABLE (1 << 7)
|
||||
# define SSI_CCR_SYNC_MASK 0x1f
|
||||
#define SSI_GDD_CICR_REG(channel) (0x804 + ((channel) * 0x40))
|
||||
# define SSI_BLOCK_IE (1 << 5)
|
||||
# define SSI_HALF_IE (1 << 2)
|
||||
# define SSI_TOUT_IE (1 << 0)
|
||||
#define SSI_GDD_CSR_REG(channel) (0x806 + ((channel) * 0x40))
|
||||
# define SSI_CSR_SYNC (1 << 6)
|
||||
# define SSI_CSR_BLOCK (1 << 5)
|
||||
# define SSI_CSR_HALF (1 << 2)
|
||||
# define SSI_CSR_TOUR (1 << 0)
|
||||
#define SSI_GDD_CSSA_REG(channel) (0x808 + ((channel) * 0x40))
|
||||
#define SSI_GDD_CDSA_REG(channel) (0x80c + ((channel) * 0x40))
|
||||
#define SSI_GDD_CEN_REG(channel) (0x810 + ((channel) * 0x40))
|
||||
#define SSI_GDD_CSAC_REG(channel) (0x818 + ((channel) * 0x40))
|
||||
#define SSI_GDD_CDAC_REG(channel) (0x81a + ((channel) * 0x40))
|
||||
#define SSI_GDD_CLNK_CTRL_REG(channel) (0x828 + ((channel) * 0x40))
|
||||
# define SSI_ENABLE_LNK (1 << 15)
|
||||
# define SSI_STOP_LNK (1 << 14)
|
||||
# define SSI_NEXT_CH_ID_MASK 0xf
|
||||
|
||||
#endif /* __OMAP_SSI_REGS_H__ */
|
||||
Loading…
Reference in New Issue