Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
ath.git patches for v5.8. Major changes: ath10k * SDIO and SNOC are not experimental anymore
This commit is contained in:
commit
b1cb6ad735
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@ -28,11 +28,10 @@ config ATH10K_AHB
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This module adds support for AHB bus
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config ATH10K_SDIO
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tristate "Atheros ath10k SDIO support (EXPERIMENTAL)"
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tristate "Atheros ath10k SDIO support"
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depends on ATH10K && MMC
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---help---
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This module adds experimental support for SDIO/MMC bus. Currently
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work in progress and will not fully work.
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This module adds support for SDIO/MMC bus.
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config ATH10K_USB
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tristate "Atheros ath10k USB support (EXPERIMENTAL)"
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@ -42,7 +41,7 @@ config ATH10K_USB
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work in progress and will not fully work.
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config ATH10K_SNOC
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tristate "Qualcomm ath10k SNOC support (EXPERIMENTAL)"
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tristate "Qualcomm ath10k SNOC support"
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depends on ATH10K
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depends on ARCH_QCOM || COMPILE_TEST
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select QCOM_QMI_HELPERS
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@ -110,7 +110,7 @@ struct ath10k_ce_ring {
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struct ce_desc_64 *shadow_base;
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/* keep last */
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void *per_transfer_context[0];
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void *per_transfer_context[];
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};
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struct ath10k_ce_pipe {
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@ -1262,7 +1262,7 @@ struct ath10k {
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int coex_gpio_pin;
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/* must be last */
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u8 drv_priv[0] __aligned(sizeof(void *));
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u8 drv_priv[] __aligned(sizeof(void *));
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};
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static inline bool ath10k_peer_stats_enabled(struct ath10k *ar)
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@ -88,7 +88,7 @@ struct ath10k_dump_file_data {
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u8 unused[128];
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/* struct ath10k_tlv_dump_data + more */
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u8 data[0];
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u8 data[];
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} __packed;
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struct ath10k_dump_ram_data_hdr {
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@ -100,7 +100,7 @@ struct ath10k_dump_ram_data_hdr {
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/* length of payload data, not including this header */
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__le32 length;
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u8 data[0];
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u8 data[];
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};
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/* magic number to fill the holes not copied due to sections in regions */
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@ -65,7 +65,7 @@ struct ath10k_pktlog_hdr {
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__le16 log_type; /* Type of log information foll this header */
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__le16 size; /* Size of variable length log information in bytes */
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__le32 timestamp;
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u8 payload[0];
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u8 payload[];
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} __packed;
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/* FIXME: How to calculate the buffer size sanely? */
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@ -289,12 +289,12 @@ struct htt_rx_ring_setup_hdr {
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struct htt_rx_ring_setup_32 {
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struct htt_rx_ring_setup_hdr hdr;
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struct htt_rx_ring_setup_ring32 rings[0];
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struct htt_rx_ring_setup_ring32 rings[];
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} __packed;
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struct htt_rx_ring_setup_64 {
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struct htt_rx_ring_setup_hdr hdr;
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struct htt_rx_ring_setup_ring64 rings[0];
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struct htt_rx_ring_setup_ring64 rings[];
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} __packed;
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/*
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@ -732,7 +732,7 @@ struct htt_rx_indication {
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* %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4)
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* and has %num_mpdu_ranges elements.
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*/
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struct htt_rx_indication_mpdu_range mpdu_ranges[0];
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struct htt_rx_indication_mpdu_range mpdu_ranges[];
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} __packed;
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/* High latency version of the RX indication */
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@ -741,7 +741,7 @@ struct htt_rx_indication_hl {
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struct htt_rx_indication_ppdu ppdu;
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struct htt_rx_indication_prefix prefix;
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struct fw_rx_desc_hl fw_desc;
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struct htt_rx_indication_mpdu_range mpdu_ranges[0];
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struct htt_rx_indication_mpdu_range mpdu_ranges[];
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} __packed;
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struct htt_hl_rx_desc {
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@ -908,7 +908,7 @@ struct htt_append_retries {
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struct htt_data_tx_completion_ext {
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struct htt_append_retries a_retries;
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__le32 t_stamp;
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__le16 msdus_rssi[0];
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__le16 msdus_rssi[];
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} __packed;
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/**
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@ -992,7 +992,7 @@ struct htt_data_tx_completion {
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} __packed;
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u8 num_msdus;
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u8 flags2; /* HTT_TX_CMPL_FLAG_DATA_RSSI */
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__le16 msdus[0]; /* variable length based on %num_msdus */
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__le16 msdus[]; /* variable length based on %num_msdus */
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} __packed;
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#define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15, 0)
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@ -1007,7 +1007,7 @@ struct htt_data_tx_ppdu_dur {
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struct htt_data_tx_compl_ppdu_dur {
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__le32 info0; /* HTT_TX_COMPL_PPDU_DUR_INFO0_ */
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struct htt_data_tx_ppdu_dur ppdu_dur[0];
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struct htt_data_tx_ppdu_dur ppdu_dur[];
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} __packed;
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struct htt_tx_compl_ind_base {
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@ -1033,7 +1033,7 @@ struct htt_rc_update {
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u8 addr[6];
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u8 num_elems;
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u8 rsvd0;
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struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */
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struct htt_rc_tx_done_params params[]; /* variable length %num_elems */
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} __packed;
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/* see htt_rx_indication for similar fields and descriptions */
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@ -1050,7 +1050,7 @@ struct htt_rx_fragment_indication {
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__le16 fw_rx_desc_bytes;
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__le16 rsvd0;
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u8 fw_msdu_rx_desc[0];
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u8 fw_msdu_rx_desc[];
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} __packed;
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#define ATH10K_IEEE80211_EXTIV BIT(5)
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@ -1075,7 +1075,7 @@ struct htt_rx_pn_ind {
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u8 seqno_end;
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u8 pn_ie_count;
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u8 reserved;
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u8 pn_ies[0];
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u8 pn_ies[];
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} __packed;
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struct htt_rx_offload_msdu {
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@ -1084,7 +1084,7 @@ struct htt_rx_offload_msdu {
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u8 vdev_id;
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u8 tid;
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u8 fw_desc;
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u8 payload[0];
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u8 payload[];
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} __packed;
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struct htt_rx_offload_ind {
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@ -1167,7 +1167,7 @@ struct htt_rx_test {
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* a) num_ints * sizeof(__le32)
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* b) num_chars * sizeof(u8) aligned to 4bytes
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*/
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u8 payload[0];
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u8 payload[];
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} __packed;
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static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test)
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@ -1201,7 +1201,7 @@ static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test)
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*/
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struct htt_pktlog_msg {
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u8 pad[3];
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u8 payload[0];
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u8 payload[];
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} __packed;
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struct htt_dbg_stats_rx_reorder_stats {
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@ -1490,7 +1490,7 @@ struct htt_stats_conf_item {
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} __packed;
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u8 pad;
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__le16 length;
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u8 payload[0]; /* roundup(length, 4) long */
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u8 payload[]; /* roundup(length, 4) long */
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} __packed;
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struct htt_stats_conf {
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@ -1499,7 +1499,7 @@ struct htt_stats_conf {
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__le32 cookie_msb;
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/* each item has variable length! */
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struct htt_stats_conf_item items[0];
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struct htt_stats_conf_item items[];
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} __packed;
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static inline struct htt_stats_conf_item *htt_stats_conf_next_item(
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@ -1673,8 +1673,8 @@ struct htt_tx_fetch_ind {
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__le32 token;
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__le16 num_resp_ids;
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__le16 num_records;
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struct htt_tx_fetch_record records[0];
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__le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */
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struct htt_tx_fetch_record records[];
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} __packed;
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static inline void *
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@ -1689,13 +1689,13 @@ struct htt_tx_fetch_resp {
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__le16 fetch_seq_num;
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__le16 num_records;
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__le32 token;
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struct htt_tx_fetch_record records[0];
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struct htt_tx_fetch_record records[];
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} __packed;
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struct htt_tx_fetch_confirm {
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u8 pad0;
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__le16 num_resp_ids;
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__le32 resp_ids[0];
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__le32 resp_ids[];
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} __packed;
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enum htt_tx_mode_switch_mode {
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@ -1727,7 +1727,7 @@ struct htt_tx_mode_switch_ind {
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__le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */
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__le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */
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u8 pad1[2];
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struct htt_tx_mode_switch_record records[0];
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struct htt_tx_mode_switch_record records[];
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} __packed;
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struct htt_channel_change {
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@ -1757,7 +1757,7 @@ struct htt_peer_tx_stats {
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u8 num_ppdu;
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u8 ppdu_len;
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u8 version;
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u8 payload[0];
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u8 payload[];
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} __packed;
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#define ATH10K_10_2_TX_STATS_OFFSET 136
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@ -2206,7 +2206,7 @@ struct htt_rx_desc {
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struct rx_ppdu_end ppdu_end;
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} __packed;
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u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN];
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u8 msdu_payload[0];
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u8 msdu_payload[];
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};
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#define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK 0x00000fff
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@ -165,7 +165,7 @@ enum qca9377_chip_id_rev {
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struct ath10k_fw_ie {
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__le32 id;
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__le32 len;
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u8 data[0];
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u8 data[];
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};
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enum ath10k_fw_ie_type {
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@ -3967,6 +3967,9 @@ void ath10k_mgmt_over_wmi_tx_work(struct work_struct *work)
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if (ret) {
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ath10k_warn(ar, "failed to transmit management frame by ref via WMI: %d\n",
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ret);
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/* remove this msdu from idr tracking */
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ath10k_wmi_cleanup_mgmt_tx_send(ar, skb);
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dma_unmap_single(ar->dev, paddr, skb->len,
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DMA_TO_DEVICE);
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ieee80211_free_txskb(ar->hw, skb);
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|
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@ -178,15 +178,16 @@ struct ath10k_pci {
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*/
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u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
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struct ce_attr *attr;
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struct ce_pipe_config *pipe_config;
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struct ce_service_to_pipe *serv_to_pipe;
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/* Keep this entry in the last, memory for struct ath10k_ahb is
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* allocated (ahb support enabled case) in the continuation of
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* this struct.
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*/
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struct ath10k_ahb ahb[0];
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struct ath10k_ahb ahb[];
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struct ce_attr *attr;
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struct ce_pipe_config *pipe_config;
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struct ce_service_to_pipe *serv_to_pipe;
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};
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static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
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|
|
|
@ -961,7 +961,16 @@ static void ath10k_qmi_del_server(struct qmi_handle *qmi_hdl,
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container_of(qmi_hdl, struct ath10k_qmi, qmi_hdl);
|
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|
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qmi->fw_ready = false;
|
||||
ath10k_qmi_driver_event_post(qmi, ATH10K_QMI_EVENT_SERVER_EXIT, NULL);
|
||||
|
||||
/*
|
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* The del_server event is to be processed only if coming from
|
||||
* the qmi server. The qmi infrastructure sends del_server, when
|
||||
* any client releases the qmi handle. In this case do not process
|
||||
* this del_server event.
|
||||
*/
|
||||
if (qmi->state == ATH10K_QMI_STATE_INIT_DONE)
|
||||
ath10k_qmi_driver_event_post(qmi, ATH10K_QMI_EVENT_SERVER_EXIT,
|
||||
NULL);
|
||||
}
|
||||
|
||||
static struct qmi_ops ath10k_qmi_ops = {
|
||||
|
@ -1046,6 +1055,7 @@ int ath10k_qmi_init(struct ath10k *ar, u32 msa_size)
|
|||
if (ret)
|
||||
goto err_qmi_lookup;
|
||||
|
||||
qmi->state = ATH10K_QMI_STATE_INIT_DONE;
|
||||
return 0;
|
||||
|
||||
err_qmi_lookup:
|
||||
|
@ -1064,6 +1074,7 @@ int ath10k_qmi_deinit(struct ath10k *ar)
|
|||
struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
|
||||
struct ath10k_qmi *qmi = ar_snoc->qmi;
|
||||
|
||||
qmi->state = ATH10K_QMI_STATE_DEINIT;
|
||||
qmi_handle_release(&qmi->qmi_hdl);
|
||||
cancel_work_sync(&qmi->event_work);
|
||||
destroy_workqueue(qmi->event_wq);
|
||||
|
|
|
@ -83,6 +83,11 @@ struct ath10k_qmi_driver_event {
|
|||
void *data;
|
||||
};
|
||||
|
||||
enum ath10k_qmi_state {
|
||||
ATH10K_QMI_STATE_INIT_DONE,
|
||||
ATH10K_QMI_STATE_DEINIT,
|
||||
};
|
||||
|
||||
struct ath10k_qmi {
|
||||
struct ath10k *ar;
|
||||
struct qmi_handle qmi_hdl;
|
||||
|
@ -102,6 +107,7 @@ struct ath10k_qmi {
|
|||
char fw_build_timestamp[MAX_TIMESTAMP_LEN + 1];
|
||||
struct ath10k_qmi_cal_data cal_data[MAX_NUM_CAL_V01];
|
||||
bool msa_fixed_perm;
|
||||
enum ath10k_qmi_state state;
|
||||
};
|
||||
|
||||
int ath10k_qmi_wlan_enable(struct ath10k *ar,
|
||||
|
|
|
@ -140,6 +140,7 @@ struct wmi_ops {
|
|||
struct sk_buff *(*gen_mgmt_tx_send)(struct ath10k *ar,
|
||||
struct sk_buff *skb,
|
||||
dma_addr_t paddr);
|
||||
int (*cleanup_mgmt_tx_send)(struct ath10k *ar, struct sk_buff *msdu);
|
||||
struct sk_buff *(*gen_dbglog_cfg)(struct ath10k *ar, u64 module_enable,
|
||||
u32 log_level);
|
||||
struct sk_buff *(*gen_pktlog_enable)(struct ath10k *ar, u32 filter);
|
||||
|
@ -448,6 +449,15 @@ ath10k_wmi_get_txbf_conf_scheme(struct ath10k *ar)
|
|||
return ar->wmi.ops->get_txbf_conf_scheme(ar);
|
||||
}
|
||||
|
||||
static inline int
|
||||
ath10k_wmi_cleanup_mgmt_tx_send(struct ath10k *ar, struct sk_buff *msdu)
|
||||
{
|
||||
if (!ar->wmi.ops->cleanup_mgmt_tx_send)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return ar->wmi.ops->cleanup_mgmt_tx_send(ar, msdu);
|
||||
}
|
||||
|
||||
static inline int
|
||||
ath10k_wmi_mgmt_tx_send(struct ath10k *ar, struct sk_buff *msdu,
|
||||
dma_addr_t paddr)
|
||||
|
|
|
@ -3010,11 +3010,23 @@ ath10k_wmi_tlv_op_gen_request_peer_stats_info(struct ath10k *ar,
|
|||
if (type == WMI_REQUEST_ONE_PEER_STATS_INFO)
|
||||
ether_addr_copy(cmd->peer_macaddr.addr, addr);
|
||||
|
||||
cmd->reset_after_request = reset;
|
||||
cmd->reset_after_request = __cpu_to_le32(reset);
|
||||
ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi tlv request peer stats info\n");
|
||||
return skb;
|
||||
}
|
||||
|
||||
static int
|
||||
ath10k_wmi_tlv_op_cleanup_mgmt_tx_send(struct ath10k *ar,
|
||||
struct sk_buff *msdu)
|
||||
{
|
||||
struct ath10k_skb_cb *cb = ATH10K_SKB_CB(msdu);
|
||||
struct ath10k_wmi *wmi = &ar->wmi;
|
||||
|
||||
idr_remove(&wmi->mgmt_pending_tx, cb->msdu_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
ath10k_wmi_mgmt_tx_alloc_msdu_id(struct ath10k *ar, struct sk_buff *skb,
|
||||
dma_addr_t paddr)
|
||||
|
@ -3089,6 +3101,8 @@ ath10k_wmi_tlv_op_gen_mgmt_tx_send(struct ath10k *ar, struct sk_buff *msdu,
|
|||
if (desc_id < 0)
|
||||
goto err_free_skb;
|
||||
|
||||
cb->msdu_id = desc_id;
|
||||
|
||||
ptr = (void *)skb->data;
|
||||
tlv = ptr;
|
||||
tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_MGMT_TX_CMD);
|
||||
|
@ -4540,6 +4554,7 @@ static const struct wmi_ops wmi_tlv_ops = {
|
|||
.gen_force_fw_hang = ath10k_wmi_tlv_op_gen_force_fw_hang,
|
||||
/* .gen_mgmt_tx = not implemented; HTT is used */
|
||||
.gen_mgmt_tx_send = ath10k_wmi_tlv_op_gen_mgmt_tx_send,
|
||||
.cleanup_mgmt_tx_send = ath10k_wmi_tlv_op_cleanup_mgmt_tx_send,
|
||||
.gen_dbglog_cfg = ath10k_wmi_tlv_op_gen_dbglog_cfg,
|
||||
.gen_pktlog_enable = ath10k_wmi_tlv_op_gen_pktlog_enable,
|
||||
.gen_pktlog_disable = ath10k_wmi_tlv_op_gen_pktlog_disable,
|
||||
|
|
|
@ -1637,7 +1637,7 @@ wmi_tlv_svc_map_ext(const __le32 *in, unsigned long *out, size_t len)
|
|||
struct wmi_tlv {
|
||||
__le16 len;
|
||||
__le16 tag;
|
||||
u8 value[0];
|
||||
u8 value[];
|
||||
} __packed;
|
||||
|
||||
struct ath10k_mgmt_tx_pkt_addr {
|
||||
|
@ -2037,7 +2037,7 @@ struct wmi_tlv_bcn_tx_status_ev {
|
|||
struct wmi_tlv_bcn_prb_info {
|
||||
__le32 caps;
|
||||
__le32 erp;
|
||||
u8 ies[0];
|
||||
u8 ies[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_tlv_bcn_tmpl_cmd {
|
||||
|
@ -2068,7 +2068,7 @@ struct wmi_tlv_diag_item {
|
|||
__le16 len;
|
||||
__le32 timestamp;
|
||||
__le32 code;
|
||||
u8 payload[0];
|
||||
u8 payload[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_tlv_diag_data_ev {
|
||||
|
|
|
@ -2292,7 +2292,7 @@ struct wmi_service_ready_event {
|
|||
* where FW can access this memory directly (or) by DMA.
|
||||
*/
|
||||
__le32 num_mem_reqs;
|
||||
struct wlan_host_mem_req mem_reqs[0];
|
||||
struct wlan_host_mem_req mem_reqs[];
|
||||
} __packed;
|
||||
|
||||
/* This is the definition from 10.X firmware branch */
|
||||
|
@ -2331,7 +2331,7 @@ struct wmi_10x_service_ready_event {
|
|||
*/
|
||||
__le32 num_mem_reqs;
|
||||
|
||||
struct wlan_host_mem_req mem_reqs[0];
|
||||
struct wlan_host_mem_req mem_reqs[];
|
||||
} __packed;
|
||||
|
||||
#define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ)
|
||||
|
@ -3086,19 +3086,19 @@ struct wmi_chan_list_entry {
|
|||
struct wmi_chan_list {
|
||||
__le32 tag; /* WMI_CHAN_LIST_TAG */
|
||||
__le32 num_chan;
|
||||
struct wmi_chan_list_entry channel_list[0];
|
||||
struct wmi_chan_list_entry channel_list[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_bssid_list {
|
||||
__le32 tag; /* WMI_BSSID_LIST_TAG */
|
||||
__le32 num_bssid;
|
||||
struct wmi_mac_addr bssid_list[0];
|
||||
struct wmi_mac_addr bssid_list[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_ie_data {
|
||||
__le32 tag; /* WMI_IE_TAG */
|
||||
__le32 ie_len;
|
||||
u8 ie_data[0];
|
||||
u8 ie_data[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_ssid {
|
||||
|
@ -3109,7 +3109,7 @@ struct wmi_ssid {
|
|||
struct wmi_ssid_list {
|
||||
__le32 tag; /* WMI_SSID_LIST_TAG */
|
||||
__le32 num_ssids;
|
||||
struct wmi_ssid ssids[0];
|
||||
struct wmi_ssid ssids[];
|
||||
} __packed;
|
||||
|
||||
/* prefix used by scan requestor ids on the host */
|
||||
|
@ -3311,7 +3311,7 @@ struct wmi_stop_scan_arg {
|
|||
|
||||
struct wmi_scan_chan_list_cmd {
|
||||
__le32 num_scan_chans;
|
||||
struct wmi_channel chan_info[0];
|
||||
struct wmi_channel chan_info[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_scan_chan_list_arg {
|
||||
|
@ -3395,12 +3395,12 @@ struct wmi_mgmt_rx_hdr_v2 {
|
|||
|
||||
struct wmi_mgmt_rx_event_v1 {
|
||||
struct wmi_mgmt_rx_hdr_v1 hdr;
|
||||
u8 buf[0];
|
||||
u8 buf[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_mgmt_rx_event_v2 {
|
||||
struct wmi_mgmt_rx_hdr_v2 hdr;
|
||||
u8 buf[0];
|
||||
u8 buf[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_10_4_mgmt_rx_hdr {
|
||||
|
@ -3415,7 +3415,7 @@ struct wmi_10_4_mgmt_rx_hdr {
|
|||
|
||||
struct wmi_10_4_mgmt_rx_event {
|
||||
struct wmi_10_4_mgmt_rx_hdr hdr;
|
||||
u8 buf[0];
|
||||
u8 buf[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_mgmt_rx_ext_info {
|
||||
|
@ -3455,14 +3455,14 @@ struct wmi_phyerr {
|
|||
__le32 rssi_chains[4];
|
||||
__le16 nf_chains[4];
|
||||
__le32 buf_len;
|
||||
u8 buf[0];
|
||||
u8 buf[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_phyerr_event {
|
||||
__le32 num_phyerrs;
|
||||
__le32 tsf_l32;
|
||||
__le32 tsf_u32;
|
||||
struct wmi_phyerr phyerrs[0];
|
||||
struct wmi_phyerr phyerrs[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_10_4_phyerr_event {
|
||||
|
@ -3479,7 +3479,7 @@ struct wmi_10_4_phyerr_event {
|
|||
__le32 phy_err_mask[2];
|
||||
__le32 tsf_timestamp;
|
||||
__le32 buf_len;
|
||||
u8 buf[0];
|
||||
u8 buf[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_radar_found_info {
|
||||
|
@ -3592,7 +3592,7 @@ struct wmi_mgmt_tx_hdr {
|
|||
|
||||
struct wmi_mgmt_tx_cmd {
|
||||
struct wmi_mgmt_tx_hdr hdr;
|
||||
u8 buf[0];
|
||||
u8 buf[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_echo_event {
|
||||
|
@ -4628,7 +4628,7 @@ struct wmi_stats_event {
|
|||
* By having a zero sized array, the pointer to data area
|
||||
* becomes available without increasing the struct size
|
||||
*/
|
||||
u8 data[0];
|
||||
u8 data[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_10_2_stats_event {
|
||||
|
@ -4638,7 +4638,7 @@ struct wmi_10_2_stats_event {
|
|||
__le32 num_vdev_stats;
|
||||
__le32 num_peer_stats;
|
||||
__le32 num_bcnflt_stats;
|
||||
u8 data[0];
|
||||
u8 data[];
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
|
@ -5033,7 +5033,7 @@ struct wmi_vdev_install_key_cmd {
|
|||
__le32 key_rxmic_len;
|
||||
|
||||
/* contains key followed by tx mic followed by rx mic */
|
||||
u8 key_data[0];
|
||||
u8 key_data[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_vdev_install_key_arg {
|
||||
|
@ -5703,7 +5703,7 @@ struct wmi_bcn_tx_hdr {
|
|||
|
||||
struct wmi_bcn_tx_cmd {
|
||||
struct wmi_bcn_tx_hdr hdr;
|
||||
u8 *bcn[0];
|
||||
u8 *bcn[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_bcn_tx_arg {
|
||||
|
@ -6120,7 +6120,7 @@ struct wmi_bcn_info {
|
|||
|
||||
struct wmi_host_swba_event {
|
||||
__le32 vdev_map;
|
||||
struct wmi_bcn_info bcn_info[0];
|
||||
struct wmi_bcn_info bcn_info[];
|
||||
} __packed;
|
||||
|
||||
struct wmi_10_2_4_bcn_info {
|
||||
|
@ -6130,7 +6130,7 @@ struct wmi_10_2_4_bcn_info {
|
|||
|
||||
struct wmi_10_2_4_host_swba_event {
|
||||
__le32 vdev_map;
|
||||
struct wmi_10_2_4_bcn_info bcn_info[0];
|
||||
struct wmi_10_2_4_bcn_info bcn_info[];
|
||||
} __packed;
|
||||
|
||||
/* 16 words = 512 client + 1 word = for guard */
|
||||
|
@ -6171,7 +6171,7 @@ struct wmi_10_4_bcn_info {
|
|||
|
||||
struct wmi_10_4_host_swba_event {
|
||||
__le32 vdev_map;
|
||||
struct wmi_10_4_bcn_info bcn_info[0];
|
||||
struct wmi_10_4_bcn_info bcn_info[];
|
||||
} __packed;
|
||||
|
||||
#define WMI_MAX_AP_VDEV 16
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/dma-mapping.h>
|
||||
#include "ahb.h"
|
||||
#include "debug.h"
|
||||
#include "hif.h"
|
||||
#include <linux/remoteproc.h>
|
||||
|
||||
static const struct of_device_id ath11k_ahb_of_match[] = {
|
||||
|
@ -434,6 +435,16 @@ enum ext_irq_num {
|
|||
tcl2host_status_ring,
|
||||
};
|
||||
|
||||
static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset)
|
||||
{
|
||||
return ioread32(ab->mem + offset);
|
||||
}
|
||||
|
||||
static inline void ath11k_ahb_write32(struct ath11k_base *ab, u32 offset, u32 value)
|
||||
{
|
||||
iowrite32(value, ab->mem + offset);
|
||||
}
|
||||
|
||||
static void ath11k_ahb_kill_tasklets(struct ath11k_base *ab)
|
||||
{
|
||||
int i;
|
||||
|
@ -575,7 +586,7 @@ static void ath11k_ahb_ce_irqs_disable(struct ath11k_base *ab)
|
|||
}
|
||||
}
|
||||
|
||||
int ath11k_ahb_start(struct ath11k_base *ab)
|
||||
static int ath11k_ahb_start(struct ath11k_base *ab)
|
||||
{
|
||||
ath11k_ahb_ce_irqs_enable(ab);
|
||||
ath11k_ce_rx_post_buf(ab);
|
||||
|
@ -583,7 +594,7 @@ int ath11k_ahb_start(struct ath11k_base *ab)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab)
|
||||
static void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
@ -595,13 +606,13 @@ void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab)
|
|||
}
|
||||
}
|
||||
|
||||
void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
|
||||
static void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
|
||||
{
|
||||
__ath11k_ahb_ext_irq_disable(ab);
|
||||
ath11k_ahb_sync_ext_irqs(ab);
|
||||
}
|
||||
|
||||
void ath11k_ahb_stop(struct ath11k_base *ab)
|
||||
static void ath11k_ahb_stop(struct ath11k_base *ab)
|
||||
{
|
||||
if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
|
||||
ath11k_ahb_ce_irqs_disable(ab);
|
||||
|
@ -611,7 +622,7 @@ void ath11k_ahb_stop(struct ath11k_base *ab)
|
|||
ath11k_ce_cleanup_pipes(ab);
|
||||
}
|
||||
|
||||
int ath11k_ahb_power_up(struct ath11k_base *ab)
|
||||
static int ath11k_ahb_power_up(struct ath11k_base *ab)
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
@ -622,7 +633,7 @@ int ath11k_ahb_power_up(struct ath11k_base *ab)
|
|||
return ret;
|
||||
}
|
||||
|
||||
void ath11k_ahb_power_down(struct ath11k_base *ab)
|
||||
static void ath11k_ahb_power_down(struct ath11k_base *ab)
|
||||
{
|
||||
rproc_shutdown(ab->tgt_rproc);
|
||||
}
|
||||
|
@ -834,8 +845,8 @@ static int ath11k_ahb_config_irq(struct ath11k_base *ab)
|
|||
return ret;
|
||||
}
|
||||
|
||||
int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
|
||||
u8 *ul_pipe, u8 *dl_pipe)
|
||||
static int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
|
||||
u8 *ul_pipe, u8 *dl_pipe)
|
||||
{
|
||||
const struct service_to_pipe *entry;
|
||||
bool ul_set = false, dl_set = false;
|
||||
|
@ -877,6 +888,18 @@ int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct ath11k_hif_ops ath11k_ahb_hif_ops = {
|
||||
.start = ath11k_ahb_start,
|
||||
.stop = ath11k_ahb_stop,
|
||||
.read32 = ath11k_ahb_read32,
|
||||
.write32 = ath11k_ahb_write32,
|
||||
.irq_enable = ath11k_ahb_ext_irq_enable,
|
||||
.irq_disable = ath11k_ahb_ext_irq_disable,
|
||||
.map_service_to_pipe = ath11k_ahb_map_service_to_pipe,
|
||||
.power_down = ath11k_ahb_power_down,
|
||||
.power_up = ath11k_ahb_power_up,
|
||||
};
|
||||
|
||||
static int ath11k_ahb_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ath11k_base *ab;
|
||||
|
@ -891,13 +914,7 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem_res) {
|
||||
dev_err(&pdev->dev, "failed to get IO memory resource\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
mem = devm_ioremap_resource(&pdev->dev, mem_res);
|
||||
mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
|
||||
if (IS_ERR(mem)) {
|
||||
dev_err(&pdev->dev, "ioremap error\n");
|
||||
return PTR_ERR(mem);
|
||||
|
@ -909,12 +926,13 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ab = ath11k_core_alloc(&pdev->dev);
|
||||
ab = ath11k_core_alloc(&pdev->dev, 0, ATH11K_BUS_AHB);
|
||||
if (!ab) {
|
||||
dev_err(&pdev->dev, "failed to allocate ath11k base\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ab->hif.ops = &ath11k_ahb_hif_ops;
|
||||
ab->pdev = pdev;
|
||||
ab->hw_rev = (enum ath11k_hw_rev)of_id->data;
|
||||
ab->mem = mem;
|
||||
|
@ -993,12 +1011,17 @@ static struct platform_driver ath11k_ahb_driver = {
|
|||
.remove = ath11k_ahb_remove,
|
||||
};
|
||||
|
||||
int ath11k_ahb_init(void)
|
||||
static int ath11k_ahb_init(void)
|
||||
{
|
||||
return platform_driver_register(&ath11k_ahb_driver);
|
||||
}
|
||||
module_init(ath11k_ahb_init);
|
||||
|
||||
void ath11k_ahb_exit(void)
|
||||
static void ath11k_ahb_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&ath11k_ahb_driver);
|
||||
}
|
||||
module_exit(ath11k_ahb_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax wireless chip");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
|
|
@ -10,26 +10,4 @@
|
|||
#define ATH11K_AHB_RECOVERY_TIMEOUT (3 * HZ)
|
||||
struct ath11k_base;
|
||||
|
||||
static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset)
|
||||
{
|
||||
return ioread32(ab->mem + offset);
|
||||
}
|
||||
|
||||
static inline void ath11k_ahb_write32(struct ath11k_base *ab, u32 offset, u32 value)
|
||||
{
|
||||
iowrite32(value, ab->mem + offset);
|
||||
}
|
||||
|
||||
void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab);
|
||||
void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab);
|
||||
int ath11k_ahb_start(struct ath11k_base *ab);
|
||||
void ath11k_ahb_stop(struct ath11k_base *ab);
|
||||
int ath11k_ahb_power_up(struct ath11k_base *ab);
|
||||
void ath11k_ahb_power_down(struct ath11k_base *ab);
|
||||
int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
|
||||
u8 *ul_pipe, u8 *dl_pipe);
|
||||
|
||||
int ath11k_ahb_init(void);
|
||||
void ath11k_ahb_exit(void);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -7,11 +7,11 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/remoteproc.h>
|
||||
#include <linux/firmware.h>
|
||||
#include "ahb.h"
|
||||
#include "core.h"
|
||||
#include "dp_tx.h"
|
||||
#include "dp_rx.h"
|
||||
#include "debug.h"
|
||||
#include "hif.h"
|
||||
|
||||
unsigned int ath11k_debug_mask;
|
||||
module_param_named(debug_mask, ath11k_debug_mask, uint, 0644);
|
||||
|
@ -41,6 +41,7 @@ u8 ath11k_core_get_hw_mac_id(struct ath11k_base *ab, int pdev_idx)
|
|||
return ATH11K_INVALID_HW_MAC_ID;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(ath11k_core_get_hw_mac_id);
|
||||
|
||||
static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name,
|
||||
size_t name_len)
|
||||
|
@ -324,7 +325,7 @@ static void ath11k_core_stop(struct ath11k_base *ab)
|
|||
{
|
||||
if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
|
||||
ath11k_qmi_firmware_stop(ab);
|
||||
ath11k_ahb_stop(ab);
|
||||
ath11k_hif_stop(ab);
|
||||
ath11k_wmi_detach(ab);
|
||||
ath11k_dp_pdev_reo_cleanup(ab);
|
||||
|
||||
|
@ -347,7 +348,7 @@ static int ath11k_core_soc_create(struct ath11k_base *ab)
|
|||
goto err_qmi_deinit;
|
||||
}
|
||||
|
||||
ret = ath11k_ahb_power_up(ab);
|
||||
ret = ath11k_hif_power_up(ab);
|
||||
if (ret) {
|
||||
ath11k_err(ab, "failed to power up :%d\n", ret);
|
||||
goto err_debugfs_reg;
|
||||
|
@ -415,7 +416,7 @@ static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
|
|||
{
|
||||
ath11k_thermal_unregister(ab);
|
||||
ath11k_mac_unregister(ab);
|
||||
ath11k_ahb_ext_irq_disable(ab);
|
||||
ath11k_hif_irq_disable(ab);
|
||||
ath11k_dp_pdev_free(ab);
|
||||
ath11k_debug_pdev_destroy(ab);
|
||||
}
|
||||
|
@ -443,7 +444,7 @@ static int ath11k_core_start(struct ath11k_base *ab,
|
|||
goto err_wmi_detach;
|
||||
}
|
||||
|
||||
ret = ath11k_ahb_start(ab);
|
||||
ret = ath11k_hif_start(ab);
|
||||
if (ret) {
|
||||
ath11k_err(ab, "failed to start HIF: %d\n", ret);
|
||||
goto err_wmi_detach;
|
||||
|
@ -522,7 +523,7 @@ err_reo_cleanup:
|
|||
err_mac_destroy:
|
||||
ath11k_mac_destroy(ab);
|
||||
err_hif_stop:
|
||||
ath11k_ahb_stop(ab);
|
||||
ath11k_hif_stop(ab);
|
||||
err_wmi_detach:
|
||||
ath11k_wmi_detach(ab);
|
||||
err_firmware_stop:
|
||||
|
@ -559,7 +560,7 @@ int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
|
|||
ath11k_err(ab, "failed to create pdev core: %d\n", ret);
|
||||
goto err_core_stop;
|
||||
}
|
||||
ath11k_ahb_ext_irq_enable(ab);
|
||||
ath11k_hif_irq_enable(ab);
|
||||
mutex_unlock(&ab->core_lock);
|
||||
|
||||
return 0;
|
||||
|
@ -579,9 +580,9 @@ static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab)
|
|||
|
||||
mutex_lock(&ab->core_lock);
|
||||
ath11k_thermal_unregister(ab);
|
||||
ath11k_ahb_ext_irq_disable(ab);
|
||||
ath11k_hif_irq_disable(ab);
|
||||
ath11k_dp_pdev_free(ab);
|
||||
ath11k_ahb_stop(ab);
|
||||
ath11k_hif_stop(ab);
|
||||
ath11k_wmi_detach(ab);
|
||||
ath11k_dp_pdev_reo_cleanup(ab);
|
||||
mutex_unlock(&ab->core_lock);
|
||||
|
@ -744,7 +745,7 @@ void ath11k_core_deinit(struct ath11k_base *ab)
|
|||
|
||||
mutex_unlock(&ab->core_lock);
|
||||
|
||||
ath11k_ahb_power_down(ab);
|
||||
ath11k_hif_power_down(ab);
|
||||
ath11k_mac_destroy(ab);
|
||||
ath11k_core_soc_destroy(ab);
|
||||
}
|
||||
|
@ -754,11 +755,12 @@ void ath11k_core_free(struct ath11k_base *ab)
|
|||
kfree(ab);
|
||||
}
|
||||
|
||||
struct ath11k_base *ath11k_core_alloc(struct device *dev)
|
||||
struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
|
||||
enum ath11k_bus bus)
|
||||
{
|
||||
struct ath11k_base *ab;
|
||||
|
||||
ab = kzalloc(sizeof(*ab), GFP_KERNEL);
|
||||
ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL);
|
||||
if (!ab)
|
||||
return NULL;
|
||||
|
||||
|
@ -784,24 +786,3 @@ err_sc_free:
|
|||
kfree(ab);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int __init ath11k_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ath11k_ahb_init();
|
||||
if (ret)
|
||||
printk(KERN_ERR "failed to register ath11k ahb driver: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
module_init(ath11k_init);
|
||||
|
||||
static void __exit ath11k_exit(void)
|
||||
{
|
||||
ath11k_ahb_exit();
|
||||
}
|
||||
module_exit(ath11k_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax wireless chip");
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
|
|
@ -607,7 +607,9 @@ struct ath11k_base {
|
|||
void __iomem *mem;
|
||||
unsigned long mem_len;
|
||||
|
||||
const struct ath11k_hif_ops *hif_ops;
|
||||
struct {
|
||||
const struct ath11k_hif_ops *ops;
|
||||
} hif;
|
||||
|
||||
struct ath11k_ce ce;
|
||||
struct timer_list rx_replenish_retry;
|
||||
|
@ -665,6 +667,9 @@ struct ath11k_base {
|
|||
|
||||
/* Round robbin based TCL ring selector */
|
||||
atomic_t tcl_ring_selector;
|
||||
|
||||
/* must be last */
|
||||
u8 drv_priv[0] __aligned(sizeof(void *));
|
||||
};
|
||||
|
||||
struct ath11k_fw_stats_pdev {
|
||||
|
@ -801,7 +806,8 @@ struct ath11k_peer *ath11k_peer_find_by_id(struct ath11k_base *ab, int peer_id);
|
|||
int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab);
|
||||
int ath11k_core_init(struct ath11k_base *ath11k);
|
||||
void ath11k_core_deinit(struct ath11k_base *ath11k);
|
||||
struct ath11k_base *ath11k_core_alloc(struct device *dev);
|
||||
struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
|
||||
enum ath11k_bus bus);
|
||||
void ath11k_core_free(struct ath11k_base *ath11k);
|
||||
int ath11k_core_fetch_bdf(struct ath11k_base *ath11k,
|
||||
struct ath11k_board_data *bd);
|
||||
|
|
|
@ -4306,6 +4306,7 @@ void ath11k_dbg_htt_ext_stats_handler(struct ath11k_base *ab,
|
|||
u32 len;
|
||||
u64 cookie;
|
||||
int ret;
|
||||
bool send_completion = false;
|
||||
u8 pdev_id;
|
||||
|
||||
msg = (struct ath11k_htt_extd_stats_msg *)skb->data;
|
||||
|
@ -4330,11 +4331,11 @@ void ath11k_dbg_htt_ext_stats_handler(struct ath11k_base *ab,
|
|||
return;
|
||||
|
||||
spin_lock_bh(&ar->debug.htt_stats.lock);
|
||||
if (stats_req->done) {
|
||||
spin_unlock_bh(&ar->debug.htt_stats.lock);
|
||||
return;
|
||||
}
|
||||
stats_req->done = true;
|
||||
|
||||
stats_req->done = FIELD_GET(HTT_T2H_EXT_STATS_INFO1_DONE, msg->info1);
|
||||
if (stats_req->done)
|
||||
send_completion = true;
|
||||
|
||||
spin_unlock_bh(&ar->debug.htt_stats.lock);
|
||||
|
||||
len = FIELD_GET(HTT_T2H_EXT_STATS_INFO1_LENGTH, msg->info1);
|
||||
|
@ -4344,7 +4345,8 @@ void ath11k_dbg_htt_ext_stats_handler(struct ath11k_base *ab,
|
|||
if (ret)
|
||||
ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
|
||||
|
||||
complete(&stats_req->cmpln);
|
||||
if (send_completion)
|
||||
complete(&stats_req->cmpln);
|
||||
}
|
||||
|
||||
static ssize_t ath11k_read_htt_stats_type(struct file *file,
|
||||
|
@ -4497,28 +4499,54 @@ static int ath11k_open_htt_stats(struct inode *inode, struct file *file)
|
|||
if (type == ATH11K_DBG_HTT_EXT_STATS_RESET)
|
||||
return -EPERM;
|
||||
|
||||
stats_req = vzalloc(sizeof(*stats_req) + ATH11K_HTT_STATS_BUF_SIZE);
|
||||
if (!stats_req)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_lock(&ar->conf_mutex);
|
||||
|
||||
if (ar->state != ATH11K_STATE_ON) {
|
||||
ret = -ENETDOWN;
|
||||
goto err_unlock;
|
||||
}
|
||||
|
||||
if (ar->debug.htt_stats.stats_req) {
|
||||
ret = -EAGAIN;
|
||||
goto err_unlock;
|
||||
}
|
||||
|
||||
stats_req = vzalloc(sizeof(*stats_req) + ATH11K_HTT_STATS_BUF_SIZE);
|
||||
if (!stats_req) {
|
||||
ret = -ENOMEM;
|
||||
goto err_unlock;
|
||||
}
|
||||
|
||||
ar->debug.htt_stats.stats_req = stats_req;
|
||||
stats_req->type = type;
|
||||
|
||||
ret = ath11k_dbg_htt_stats_req(ar);
|
||||
mutex_unlock(&ar->conf_mutex);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
file->private_data = stats_req;
|
||||
|
||||
mutex_unlock(&ar->conf_mutex);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
vfree(stats_req);
|
||||
ar->debug.htt_stats.stats_req = NULL;
|
||||
err_unlock:
|
||||
mutex_unlock(&ar->conf_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ath11k_release_htt_stats(struct inode *inode, struct file *file)
|
||||
{
|
||||
struct ath11k *ar = inode->i_private;
|
||||
|
||||
mutex_lock(&ar->conf_mutex);
|
||||
vfree(file->private_data);
|
||||
ar->debug.htt_stats.stats_req = NULL;
|
||||
mutex_unlock(&ar->conf_mutex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -701,6 +701,7 @@ int ath11k_dp_service_srng(struct ath11k_base *ab,
|
|||
done:
|
||||
return tot_work_done;
|
||||
}
|
||||
EXPORT_SYMBOL(ath11k_dp_service_srng);
|
||||
|
||||
void ath11k_dp_pdev_free(struct ath11k_base *ab)
|
||||
{
|
||||
|
|
|
@ -1517,6 +1517,7 @@ struct htt_ext_stats_cfg_params {
|
|||
* 4 bytes.
|
||||
*/
|
||||
|
||||
#define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11)
|
||||
#define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16)
|
||||
|
||||
struct ath11k_htt_extd_stats_msg {
|
||||
|
|
|
@ -2728,7 +2728,7 @@ static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
|
|||
ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
|
||||
buf_id);
|
||||
spin_unlock_bh(&rx_ring->idr_lock);
|
||||
continue;
|
||||
goto move_next;
|
||||
}
|
||||
|
||||
idr_remove(&rx_ring->bufs_idr, buf_id);
|
||||
|
@ -2747,13 +2747,16 @@ static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
|
|||
tlv = (struct hal_tlv_hdr *)skb->data;
|
||||
if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
|
||||
HAL_RX_STATUS_BUFFER_DONE) {
|
||||
ath11k_hal_srng_src_get_next_entry(ab, srng);
|
||||
continue;
|
||||
ath11k_warn(ab, "mon status DONE not set %lx\n",
|
||||
FIELD_GET(HAL_TLV_HDR_TAG,
|
||||
tlv->tl));
|
||||
dev_kfree_skb_any(skb);
|
||||
goto move_next;
|
||||
}
|
||||
|
||||
__skb_queue_tail(skb_list, skb);
|
||||
}
|
||||
|
||||
move_next:
|
||||
skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
|
||||
&buf_id, GFP_ATOMIC);
|
||||
|
||||
|
|
|
@ -3,10 +3,10 @@
|
|||
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
#include <linux/dma-mapping.h>
|
||||
#include "ahb.h"
|
||||
#include "hal_tx.h"
|
||||
#include "debug.h"
|
||||
#include "hal_desc.h"
|
||||
#include "hif.h"
|
||||
|
||||
static const struct hal_srng_config hw_srng_config[] = {
|
||||
/* TODO: max_rings can populated by querying HW capabilities */
|
||||
|
@ -351,11 +351,12 @@ static void ath11k_hal_ce_dst_setup(struct ath11k_base *ab,
|
|||
addr = HAL_CE_DST_RING_CTRL +
|
||||
srng_config->reg_start[HAL_SRNG_REG_GRP_R0] +
|
||||
ring_num * srng_config->reg_size[HAL_SRNG_REG_GRP_R0];
|
||||
val = ath11k_ahb_read32(ab, addr);
|
||||
|
||||
val = ath11k_hif_read32(ab, addr);
|
||||
val &= ~HAL_CE_DST_R0_DEST_CTRL_MAX_LEN;
|
||||
val |= FIELD_PREP(HAL_CE_DST_R0_DEST_CTRL_MAX_LEN,
|
||||
srng->u.dst_ring.max_buffer_length);
|
||||
ath11k_ahb_write32(ab, addr, val);
|
||||
ath11k_hif_write32(ab, addr, val);
|
||||
}
|
||||
|
||||
static void ath11k_hal_srng_dst_hw_init(struct ath11k_base *ab,
|
||||
|
@ -369,34 +370,34 @@ static void ath11k_hal_srng_dst_hw_init(struct ath11k_base *ab,
|
|||
reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
|
||||
|
||||
if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) {
|
||||
ath11k_ahb_write32(ab, reg_base +
|
||||
HAL_REO1_RING_MSI1_BASE_LSB_OFFSET,
|
||||
ath11k_hif_write32(ab, reg_base +
|
||||
HAL_REO1_RING_MSI1_BASE_LSB_OFFSET,
|
||||
(u32)srng->msi_addr);
|
||||
|
||||
val = FIELD_PREP(HAL_REO1_RING_MSI1_BASE_MSB_ADDR,
|
||||
((u64)srng->msi_addr >>
|
||||
HAL_ADDR_MSB_REG_SHIFT)) |
|
||||
HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE;
|
||||
ath11k_ahb_write32(ab, reg_base +
|
||||
ath11k_hif_write32(ab, reg_base +
|
||||
HAL_REO1_RING_MSI1_BASE_MSB_OFFSET, val);
|
||||
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
reg_base + HAL_REO1_RING_MSI1_DATA_OFFSET,
|
||||
srng->msi_data);
|
||||
}
|
||||
|
||||
ath11k_ahb_write32(ab, reg_base, (u32)srng->ring_base_paddr);
|
||||
ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr);
|
||||
|
||||
val = FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
|
||||
((u64)srng->ring_base_paddr >>
|
||||
HAL_ADDR_MSB_REG_SHIFT)) |
|
||||
FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_SIZE,
|
||||
(srng->entry_size * srng->num_entries));
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET, val);
|
||||
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET, val);
|
||||
|
||||
val = FIELD_PREP(HAL_REO1_RING_ID_RING_ID, srng->ring_id) |
|
||||
FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size);
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET, val);
|
||||
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET, val);
|
||||
|
||||
/* interrupt setup */
|
||||
val = FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD,
|
||||
|
@ -406,22 +407,22 @@ static void ath11k_hal_srng_dst_hw_init(struct ath11k_base *ab,
|
|||
(srng->intr_batch_cntr_thres_entries *
|
||||
srng->entry_size));
|
||||
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET,
|
||||
val);
|
||||
|
||||
hp_addr = hal->rdp.paddr +
|
||||
((unsigned long)srng->u.dst_ring.hp_addr -
|
||||
(unsigned long)hal->rdp.vaddr);
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET,
|
||||
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET,
|
||||
hp_addr & HAL_ADDR_LSB_REG_MASK);
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET,
|
||||
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET,
|
||||
hp_addr >> HAL_ADDR_MSB_REG_SHIFT);
|
||||
|
||||
/* Initialize head and tail pointers to indicate ring is empty */
|
||||
reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2];
|
||||
ath11k_ahb_write32(ab, reg_base, 0);
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET, 0);
|
||||
ath11k_hif_write32(ab, reg_base, 0);
|
||||
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET, 0);
|
||||
*srng->u.dst_ring.hp_addr = 0;
|
||||
|
||||
reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
|
||||
|
@ -434,7 +435,7 @@ static void ath11k_hal_srng_dst_hw_init(struct ath11k_base *ab,
|
|||
val |= HAL_REO1_RING_MISC_MSI_SWAP;
|
||||
val |= HAL_REO1_RING_MISC_SRNG_ENABLE;
|
||||
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET, val);
|
||||
ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET, val);
|
||||
}
|
||||
|
||||
static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
|
||||
|
@ -448,34 +449,34 @@ static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
|
|||
reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
|
||||
|
||||
if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) {
|
||||
ath11k_ahb_write32(ab, reg_base +
|
||||
HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET,
|
||||
ath11k_hif_write32(ab, reg_base +
|
||||
HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET,
|
||||
(u32)srng->msi_addr);
|
||||
|
||||
val = FIELD_PREP(HAL_TCL1_RING_MSI1_BASE_MSB_ADDR,
|
||||
((u64)srng->msi_addr >>
|
||||
HAL_ADDR_MSB_REG_SHIFT)) |
|
||||
HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE;
|
||||
ath11k_ahb_write32(ab, reg_base +
|
||||
ath11k_hif_write32(ab, reg_base +
|
||||
HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET,
|
||||
val);
|
||||
|
||||
ath11k_ahb_write32(ab, reg_base +
|
||||
ath11k_hif_write32(ab, reg_base +
|
||||
HAL_TCL1_RING_MSI1_DATA_OFFSET,
|
||||
srng->msi_data);
|
||||
}
|
||||
|
||||
ath11k_ahb_write32(ab, reg_base, (u32)srng->ring_base_paddr);
|
||||
ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr);
|
||||
|
||||
val = FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB,
|
||||
((u64)srng->ring_base_paddr >>
|
||||
HAL_ADDR_MSB_REG_SHIFT)) |
|
||||
FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE,
|
||||
(srng->entry_size * srng->num_entries));
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET, val);
|
||||
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET, val);
|
||||
|
||||
val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size);
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET, val);
|
||||
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET, val);
|
||||
|
||||
/* interrupt setup */
|
||||
/* NOTE: IPQ8074 v2 requires the interrupt timer threshold in the
|
||||
|
@ -488,7 +489,7 @@ static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
|
|||
(srng->intr_batch_cntr_thres_entries *
|
||||
srng->entry_size));
|
||||
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET,
|
||||
val);
|
||||
|
||||
|
@ -497,7 +498,7 @@ static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
|
|||
val |= FIELD_PREP(HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD,
|
||||
srng->u.src_ring.low_threshold);
|
||||
}
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET,
|
||||
val);
|
||||
|
||||
|
@ -505,18 +506,18 @@ static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
|
|||
tp_addr = hal->rdp.paddr +
|
||||
((unsigned long)srng->u.src_ring.tp_addr -
|
||||
(unsigned long)hal->rdp.vaddr);
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
reg_base + HAL_TCL1_RING_TP_ADDR_LSB_OFFSET,
|
||||
tp_addr & HAL_ADDR_LSB_REG_MASK);
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
reg_base + HAL_TCL1_RING_TP_ADDR_MSB_OFFSET,
|
||||
tp_addr >> HAL_ADDR_MSB_REG_SHIFT);
|
||||
}
|
||||
|
||||
/* Initialize head and tail pointers to indicate ring is empty */
|
||||
reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2];
|
||||
ath11k_ahb_write32(ab, reg_base, 0);
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0);
|
||||
ath11k_hif_write32(ab, reg_base, 0);
|
||||
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0);
|
||||
*srng->u.src_ring.tp_addr = 0;
|
||||
|
||||
reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0];
|
||||
|
@ -533,7 +534,7 @@ static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab,
|
|||
|
||||
val |= HAL_TCL1_RING_MISC_SRNG_ENABLE;
|
||||
|
||||
ath11k_ahb_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET, val);
|
||||
ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET, val);
|
||||
}
|
||||
|
||||
static void ath11k_hal_srng_hw_init(struct ath11k_base *ab,
|
||||
|
@ -889,13 +890,13 @@ void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng)
|
|||
if (srng->ring_dir == HAL_SRNG_DIR_SRC) {
|
||||
srng->u.src_ring.last_tp =
|
||||
*(volatile u32 *)srng->u.src_ring.tp_addr;
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
(unsigned long)srng->u.src_ring.hp_addr -
|
||||
(unsigned long)ab->mem,
|
||||
srng->u.src_ring.hp);
|
||||
} else {
|
||||
srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr;
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
(unsigned long)srng->u.dst_ring.tp_addr -
|
||||
(unsigned long)ab->mem,
|
||||
srng->u.dst_ring.tp);
|
||||
|
@ -929,20 +930,20 @@ void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
|
|||
HAL_WBM_IDLE_SCATTER_BUF_SIZE;
|
||||
}
|
||||
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR,
|
||||
FIELD_PREP(HAL_WBM_SCATTER_BUFFER_SIZE, reg_scatter_buf_sz) |
|
||||
FIELD_PREP(HAL_WBM_LINK_DESC_IDLE_LIST_MODE, 0x1));
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_R0_IDLE_LIST_SIZE_ADDR,
|
||||
FIELD_PREP(HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
|
||||
reg_scatter_buf_sz * nsbufs));
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG +
|
||||
HAL_WBM_SCATTERED_RING_BASE_LSB,
|
||||
FIELD_PREP(BUFFER_ADDR_INFO0_ADDR,
|
||||
sbuf[0].paddr & HAL_ADDR_LSB_REG_MASK));
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG +
|
||||
HAL_WBM_SCATTERED_RING_BASE_MSB,
|
||||
FIELD_PREP(
|
||||
|
@ -953,12 +954,12 @@ void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
|
|||
BASE_ADDR_MATCH_TAG_VAL));
|
||||
|
||||
/* Setup head and tail pointers for the idle list */
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG +
|
||||
HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0,
|
||||
FIELD_PREP(BUFFER_ADDR_INFO0_ADDR,
|
||||
sbuf[nsbufs - 1].paddr));
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG +
|
||||
HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1,
|
||||
FIELD_PREP(
|
||||
|
@ -967,18 +968,18 @@ void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
|
|||
HAL_ADDR_MSB_REG_SHIFT)) |
|
||||
FIELD_PREP(HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1,
|
||||
(end_offset >> 2)));
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG +
|
||||
HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0,
|
||||
FIELD_PREP(BUFFER_ADDR_INFO0_ADDR,
|
||||
sbuf[0].paddr));
|
||||
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG +
|
||||
HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0,
|
||||
FIELD_PREP(BUFFER_ADDR_INFO0_ADDR,
|
||||
sbuf[0].paddr));
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG +
|
||||
HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1,
|
||||
FIELD_PREP(
|
||||
|
@ -986,13 +987,13 @@ void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
|
|||
((u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT)) |
|
||||
FIELD_PREP(HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1,
|
||||
0));
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG +
|
||||
HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR,
|
||||
2 * tot_link_desc);
|
||||
|
||||
/* Enable the SRNG */
|
||||
ath11k_ahb_write32(ab,
|
||||
ath11k_hif_write32(ab,
|
||||
HAL_SEQ_WCSS_UMAC_WBM_REG +
|
||||
HAL_WBM_IDLE_LINK_RING_MISC_ADDR, 0x40);
|
||||
}
|
||||
|
|
|
@ -2,6 +2,8 @@
|
|||
/*
|
||||
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
#include "core.h"
|
||||
|
||||
#ifndef ATH11K_HAL_DESC_H
|
||||
#define ATH11K_HAL_DESC_H
|
||||
|
||||
|
|
|
@ -3,12 +3,12 @@
|
|||
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "ahb.h"
|
||||
#include "debug.h"
|
||||
#include "hal.h"
|
||||
#include "hal_tx.h"
|
||||
#include "hal_rx.h"
|
||||
#include "hal_desc.h"
|
||||
#include "hif.h"
|
||||
|
||||
static void ath11k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr,
|
||||
u8 owner, u8 buffer_type, u32 magic)
|
||||
|
@ -804,34 +804,34 @@ void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map)
|
|||
u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
|
||||
u32 val;
|
||||
|
||||
val = ath11k_ahb_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
|
||||
val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
|
||||
|
||||
val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
|
||||
val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
|
||||
HAL_SRNG_RING_ID_REO2SW1) |
|
||||
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
|
||||
FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
|
||||
ath11k_ahb_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
|
||||
|
||||
ath11k_ahb_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0,
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0,
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_ahb_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1,
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1,
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_ahb_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2,
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2,
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
ath11k_ahb_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3,
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3,
|
||||
HAL_DEFAULT_REO_TIMEOUT_USEC);
|
||||
|
||||
ath11k_ahb_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
ath11k_ahb_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
ath11k_ahb_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
ath11k_ahb_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
|
||||
ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
|
||||
FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
|
||||
ring_hash_map));
|
||||
}
|
||||
|
|
|
@ -3,9 +3,10 @@
|
|||
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "ahb.h"
|
||||
#include "hal_desc.h"
|
||||
#include "hal.h"
|
||||
#include "hal_tx.h"
|
||||
#include "hif.h"
|
||||
|
||||
#define DSCP_TID_MAP_TBL_ENTRY_SIZE 64
|
||||
|
||||
|
@ -83,11 +84,11 @@ void ath11k_hal_tx_set_dscp_tid_map(struct ath11k_base *ab, int id)
|
|||
u32 value;
|
||||
int cnt = 0;
|
||||
|
||||
ctrl_reg_val = ath11k_ahb_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
|
||||
ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
|
||||
HAL_TCL1_RING_CMN_CTRL_REG);
|
||||
/* Enable read/write access */
|
||||
ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
|
||||
ath11k_ahb_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
|
||||
ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
|
||||
HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val);
|
||||
|
||||
addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP +
|
||||
|
@ -118,15 +119,15 @@ void ath11k_hal_tx_set_dscp_tid_map(struct ath11k_base *ab, int id)
|
|||
}
|
||||
|
||||
for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) {
|
||||
ath11k_ahb_write32(ab, addr, *(u32 *)&hw_map_val[i]);
|
||||
ath11k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]);
|
||||
addr += 4;
|
||||
}
|
||||
|
||||
/* Disable read/write access */
|
||||
ctrl_reg_val = ath11k_ahb_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
|
||||
ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
|
||||
HAL_TCL1_RING_CMN_CTRL_REG);
|
||||
ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
|
||||
ath11k_ahb_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
|
||||
ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
|
||||
HAL_TCL1_RING_CMN_CTRL_REG,
|
||||
ctrl_reg_val);
|
||||
}
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
#define ATH11K_HAL_TX_H
|
||||
|
||||
#include "hal_desc.h"
|
||||
#include "core.h"
|
||||
|
||||
#define HAL_TX_ADDRX_EN 1
|
||||
#define HAL_TX_ADDRY_EN 2
|
||||
|
|
|
@ -0,0 +1,65 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
|
||||
/*
|
||||
* Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "core.h"
|
||||
|
||||
struct ath11k_hif_ops {
|
||||
u32 (*read32)(struct ath11k_base *sc, u32 address);
|
||||
void (*write32)(struct ath11k_base *sc, u32 address, u32 data);
|
||||
void (*irq_enable)(struct ath11k_base *sc);
|
||||
void (*irq_disable)(struct ath11k_base *sc);
|
||||
int (*start)(struct ath11k_base *sc);
|
||||
void (*stop)(struct ath11k_base *sc);
|
||||
int (*power_up)(struct ath11k_base *sc);
|
||||
void (*power_down)(struct ath11k_base *sc);
|
||||
int (*map_service_to_pipe)(struct ath11k_base *sc, u16 service_id,
|
||||
u8 *ul_pipe, u8 *dl_pipe);
|
||||
};
|
||||
|
||||
static inline int ath11k_hif_start(struct ath11k_base *sc)
|
||||
{
|
||||
return sc->hif.ops->start(sc);
|
||||
}
|
||||
|
||||
static inline void ath11k_hif_stop(struct ath11k_base *sc)
|
||||
{
|
||||
sc->hif.ops->stop(sc);
|
||||
}
|
||||
|
||||
static inline void ath11k_hif_irq_enable(struct ath11k_base *sc)
|
||||
{
|
||||
sc->hif.ops->irq_enable(sc);
|
||||
}
|
||||
|
||||
static inline void ath11k_hif_irq_disable(struct ath11k_base *sc)
|
||||
{
|
||||
sc->hif.ops->irq_disable(sc);
|
||||
}
|
||||
|
||||
static inline int ath11k_hif_power_up(struct ath11k_base *sc)
|
||||
{
|
||||
return sc->hif.ops->power_up(sc);
|
||||
}
|
||||
|
||||
static inline void ath11k_hif_power_down(struct ath11k_base *sc)
|
||||
{
|
||||
sc->hif.ops->power_down(sc);
|
||||
}
|
||||
|
||||
static inline u32 ath11k_hif_read32(struct ath11k_base *sc, u32 address)
|
||||
{
|
||||
return sc->hif.ops->read32(sc, address);
|
||||
}
|
||||
|
||||
static inline void ath11k_hif_write32(struct ath11k_base *sc, u32 address, u32 data)
|
||||
{
|
||||
sc->hif.ops->write32(sc, address, data);
|
||||
}
|
||||
|
||||
static inline int ath11k_hif_map_service_to_pipe(struct ath11k_base *sc, u16 service_id,
|
||||
u8 *ul_pipe, u8 *dl_pipe)
|
||||
{
|
||||
return sc->hif.ops->map_service_to_pipe(sc, service_id, ul_pipe, dl_pipe);
|
||||
}
|
|
@ -5,8 +5,8 @@
|
|||
#include <linux/skbuff.h>
|
||||
#include <linux/ctype.h>
|
||||
|
||||
#include "ahb.h"
|
||||
#include "debug.h"
|
||||
#include "hif.h"
|
||||
|
||||
struct sk_buff *ath11k_htc_alloc_skb(struct ath11k_base *ab, int size)
|
||||
{
|
||||
|
@ -672,7 +672,7 @@ setup:
|
|||
/* copy all the callbacks */
|
||||
ep->ep_ops = conn_req->ep_ops;
|
||||
|
||||
status = ath11k_ahb_map_service_to_pipe(htc->ab,
|
||||
status = ath11k_hif_map_service_to_pipe(htc->ab,
|
||||
ep->service_id,
|
||||
&ep->ul_pipe_id,
|
||||
&ep->dl_pipe_id);
|
||||
|
|
|
@ -99,6 +99,11 @@ enum ath11k_hw_rate_ofdm {
|
|||
ATH11K_HW_RATE_OFDM_9M,
|
||||
};
|
||||
|
||||
enum ath11k_bus {
|
||||
ATH11K_BUS_AHB,
|
||||
ATH11K_BUS_PCI,
|
||||
};
|
||||
|
||||
struct ath11k_hw_params {
|
||||
const char *name;
|
||||
struct {
|
||||
|
|
|
@ -3692,7 +3692,7 @@ static int __ath11k_set_antenna(struct ath11k *ar, u32 tx_ant, u32 rx_ant)
|
|||
int ath11k_mac_tx_mgmt_pending_free(int buf_id, void *skb, void *ctx)
|
||||
{
|
||||
struct sk_buff *msdu = skb;
|
||||
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu);
|
||||
struct ieee80211_tx_info *info;
|
||||
struct ath11k *ar = ctx;
|
||||
struct ath11k_base *ab = ar->ab;
|
||||
|
||||
|
|
|
@ -174,9 +174,12 @@ int ath11k_thermal_register(struct ath11k_base *sc)
|
|||
if (IS_ERR(cdev)) {
|
||||
ath11k_err(sc, "failed to setup thermal device result: %ld\n",
|
||||
PTR_ERR(cdev));
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
goto err_thermal_destroy;
|
||||
}
|
||||
|
||||
ar->thermal.cdev = cdev;
|
||||
|
||||
ret = sysfs_create_link(&ar->hw->wiphy->dev.kobj, &cdev->device.kobj,
|
||||
"cooling_device");
|
||||
if (ret) {
|
||||
|
@ -184,7 +187,6 @@ int ath11k_thermal_register(struct ath11k_base *sc)
|
|||
goto err_thermal_destroy;
|
||||
}
|
||||
|
||||
ar->thermal.cdev = cdev;
|
||||
if (!IS_REACHABLE(CONFIG_HWMON))
|
||||
return 0;
|
||||
|
||||
|
|
|
@ -127,7 +127,7 @@ struct carl9170_write_reg {
|
|||
struct carl9170_write_reg_byte {
|
||||
__le32 addr;
|
||||
__le32 count;
|
||||
u8 val[0];
|
||||
u8 val[];
|
||||
} __packed;
|
||||
|
||||
#define CARL9170FW_PHY_HT_ENABLE 0x4
|
||||
|
|
|
@ -851,7 +851,7 @@ struct ar9170_stream {
|
|||
__le16 length;
|
||||
__le16 tag;
|
||||
|
||||
u8 payload[0];
|
||||
u8 payload[];
|
||||
} __packed __aligned(4);
|
||||
#define AR9170_STREAM_LEN 4
|
||||
|
||||
|
|
|
@ -2240,7 +2240,7 @@ struct wcn36xx_hal_process_ptt_msg_req_msg {
|
|||
struct wcn36xx_hal_msg_header header;
|
||||
|
||||
/* Actual FTM Command body */
|
||||
u8 ptt_msg[0];
|
||||
u8 ptt_msg[];
|
||||
} __packed;
|
||||
|
||||
struct wcn36xx_hal_process_ptt_msg_rsp_msg {
|
||||
|
@ -2249,7 +2249,7 @@ struct wcn36xx_hal_process_ptt_msg_rsp_msg {
|
|||
/* FTM Command response status */
|
||||
u32 ptt_msg_resp_status;
|
||||
/* Actual FTM Command body */
|
||||
u8 ptt_msg[0];
|
||||
u8 ptt_msg[];
|
||||
} __packed;
|
||||
|
||||
struct update_edca_params_req_msg {
|
||||
|
|
|
@ -1339,7 +1339,7 @@ static int wcn36xx_probe(struct platform_device *pdev)
|
|||
if (addr && ret != ETH_ALEN) {
|
||||
wcn36xx_err("invalid local-mac-address\n");
|
||||
ret = -EINVAL;
|
||||
goto out_wq;
|
||||
goto out_destroy_ept;
|
||||
} else if (addr) {
|
||||
wcn36xx_info("mac address: %pM\n", addr);
|
||||
SET_IEEE80211_PERM_ADDR(wcn->hw, addr);
|
||||
|
@ -1347,7 +1347,7 @@ static int wcn36xx_probe(struct platform_device *pdev)
|
|||
|
||||
ret = wcn36xx_platform_get_resources(wcn, pdev);
|
||||
if (ret)
|
||||
goto out_wq;
|
||||
goto out_destroy_ept;
|
||||
|
||||
wcn36xx_init_ieee80211(wcn);
|
||||
ret = ieee80211_register_hw(wcn->hw);
|
||||
|
@ -1359,6 +1359,8 @@ static int wcn36xx_probe(struct platform_device *pdev)
|
|||
out_unmap:
|
||||
iounmap(wcn->ccu_base);
|
||||
iounmap(wcn->dxe_base);
|
||||
out_destroy_ept:
|
||||
rpmsg_destroy_ept(wcn->smd_channel);
|
||||
out_wq:
|
||||
ieee80211_free_hw(hw);
|
||||
out_err:
|
||||
|
|
|
@ -20,7 +20,7 @@ struct ftm_rsp_msg {
|
|||
u16 msg_id;
|
||||
u16 msg_body_length;
|
||||
u32 resp_status;
|
||||
u8 msg_response[0];
|
||||
u8 msg_response[];
|
||||
} __packed;
|
||||
|
||||
/* The request buffer of FTM which contains a byte of command and the request */
|
||||
|
|
|
@ -33,7 +33,7 @@ struct wil_fw_record_head {
|
|||
*/
|
||||
struct wil_fw_record_data { /* type == wil_fw_type_data */
|
||||
__le32 addr;
|
||||
__le32 data[0]; /* [data_size], see above */
|
||||
__le32 data[]; /* [data_size], see above */
|
||||
} __packed;
|
||||
|
||||
/* fill with constant @value, @size bytes starting from @addr */
|
||||
|
@ -61,7 +61,7 @@ struct wil_fw_record_capabilities { /* type == wil_fw_type_comment */
|
|||
/* identifies capabilities record */
|
||||
struct wil_fw_record_comment_hdr hdr;
|
||||
/* capabilities (variable size), see enum wmi_fw_capability */
|
||||
u8 capabilities[0];
|
||||
u8 capabilities[];
|
||||
} __packed;
|
||||
|
||||
/* FW VIF concurrency encoded inside a comment record
|
||||
|
@ -80,7 +80,7 @@ struct wil_fw_concurrency_combo {
|
|||
u8 n_diff_channels; /* total number of different channels allowed */
|
||||
u8 same_bi; /* for APs, 1 if all APs must have same BI */
|
||||
/* keep last - concurrency limits, variable size by n_limits */
|
||||
struct wil_fw_concurrency_limit limits[0];
|
||||
struct wil_fw_concurrency_limit limits[];
|
||||
} __packed;
|
||||
|
||||
struct wil_fw_record_concurrency { /* type == wil_fw_type_comment */
|
||||
|
@ -93,7 +93,7 @@ struct wil_fw_record_concurrency { /* type == wil_fw_type_comment */
|
|||
/* number of concurrency combinations that follow */
|
||||
__le16 n_combos;
|
||||
/* keep last - combinations, variable size by n_combos */
|
||||
struct wil_fw_concurrency_combo combos[0];
|
||||
struct wil_fw_concurrency_combo combos[];
|
||||
} __packed;
|
||||
|
||||
/* brd file info encoded inside a comment record */
|
||||
|
@ -108,7 +108,7 @@ struct wil_fw_record_brd_file { /* type == wil_fw_type_comment */
|
|||
/* identifies brd file record */
|
||||
struct wil_fw_record_comment_hdr hdr;
|
||||
__le32 version;
|
||||
struct brd_info brd_info[0];
|
||||
struct brd_info brd_info[];
|
||||
} __packed;
|
||||
|
||||
/* perform action
|
||||
|
@ -116,7 +116,7 @@ struct wil_fw_record_brd_file { /* type == wil_fw_type_comment */
|
|||
*/
|
||||
struct wil_fw_record_action { /* type == wil_fw_type_action */
|
||||
__le32 action; /* action to perform: reset, wait for fw ready etc. */
|
||||
__le32 data[0]; /* action specific, [data_size], see above */
|
||||
__le32 data[]; /* action specific, [data_size], see above */
|
||||
} __packed;
|
||||
|
||||
/* data block for struct wil_fw_record_direct_write */
|
||||
|
@ -179,7 +179,7 @@ struct wil_fw_record_gateway_data { /* type == wil_fw_type_gateway_data */
|
|||
#define WIL_FW_GW_CTL_BUSY BIT(29) /* gateway busy performing operation */
|
||||
#define WIL_FW_GW_CTL_RUN BIT(30) /* start gateway operation */
|
||||
__le32 command;
|
||||
struct wil_fw_data_gw data[0]; /* total size [data_size], see above */
|
||||
struct wil_fw_data_gw data[]; /* total size [data_size], see above */
|
||||
} __packed;
|
||||
|
||||
/* 4-dword gateway */
|
||||
|
@ -201,7 +201,7 @@ struct wil_fw_record_gateway_data4 { /* type == wil_fw_type_gateway_data4 */
|
|||
__le32 gateway_cmd_addr;
|
||||
__le32 gateway_ctrl_address; /* same logic as for 1-dword gw */
|
||||
__le32 command;
|
||||
struct wil_fw_data_gw4 data[0]; /* total size [data_size], see above */
|
||||
struct wil_fw_data_gw4 data[]; /* total size [data_size], see above */
|
||||
} __packed;
|
||||
|
||||
#endif /* __WIL_FW_H__ */
|
||||
|
|
|
@ -222,7 +222,7 @@ struct auth_no_hdr {
|
|||
__le16 auth_transaction;
|
||||
__le16 status_code;
|
||||
/* possibly followed by Challenge text */
|
||||
u8 variable[0];
|
||||
u8 variable[];
|
||||
} __packed;
|
||||
|
||||
u8 led_polarity = LED_POLARITY_LOW_ACTIVE;
|
||||
|
|
|
@ -474,7 +474,7 @@ struct wmi_start_scan_cmd {
|
|||
struct {
|
||||
u8 channel;
|
||||
u8 reserved;
|
||||
} channel_list[0];
|
||||
} channel_list[];
|
||||
} __packed;
|
||||
|
||||
#define WMI_MAX_PNO_SSID_NUM (16)
|
||||
|
@ -530,7 +530,7 @@ struct wmi_update_ft_ies_cmd {
|
|||
/* Length of the FT IEs */
|
||||
__le16 ie_len;
|
||||
u8 reserved[2];
|
||||
u8 ie_info[0];
|
||||
u8 ie_info[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_SET_PROBED_SSID_CMDID */
|
||||
|
@ -575,7 +575,7 @@ struct wmi_set_appie_cmd {
|
|||
u8 reserved;
|
||||
/* Length of the IE to be added to MGMT frame */
|
||||
__le16 ie_len;
|
||||
u8 ie_info[0];
|
||||
u8 ie_info[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_PXMT_RANGE_CFG_CMDID */
|
||||
|
@ -850,7 +850,7 @@ struct wmi_pcp_start_cmd {
|
|||
struct wmi_sw_tx_req_cmd {
|
||||
u8 dst_mac[WMI_MAC_LEN];
|
||||
__le16 len;
|
||||
u8 payload[0];
|
||||
u8 payload[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_SW_TX_REQ_EXT_CMDID */
|
||||
|
@ -861,7 +861,7 @@ struct wmi_sw_tx_req_ext_cmd {
|
|||
/* Channel to use, 0xFF for currently active channel */
|
||||
u8 channel;
|
||||
u8 reserved[5];
|
||||
u8 payload[0];
|
||||
u8 payload[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_VRING_SWITCH_TIMING_CONFIG_CMDID */
|
||||
|
@ -1423,7 +1423,7 @@ struct wmi_rf_xpm_write_cmd {
|
|||
u8 verify;
|
||||
u8 reserved1[3];
|
||||
/* actual size=num_bytes */
|
||||
u8 data_bytes[0];
|
||||
u8 data_bytes[];
|
||||
} __packed;
|
||||
|
||||
/* Possible modes for temperature measurement */
|
||||
|
@ -1572,7 +1572,7 @@ struct wmi_tof_session_start_cmd {
|
|||
u8 aoa_type;
|
||||
__le16 num_of_dest;
|
||||
u8 reserved[4];
|
||||
struct wmi_ftm_dest_info ftm_dest_info[0];
|
||||
struct wmi_ftm_dest_info ftm_dest_info[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_TOF_CFG_RESPONDER_CMDID */
|
||||
|
@ -1766,7 +1766,7 @@ struct wmi_internal_fw_ioctl_cmd {
|
|||
/* payload max size is WMI_MAX_IOCTL_PAYLOAD_SIZE
|
||||
* Must be the last member of the struct
|
||||
*/
|
||||
__le32 payload[0];
|
||||
__le32 payload[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_INTERNAL_FW_IOCTL_EVENTID */
|
||||
|
@ -1778,7 +1778,7 @@ struct wmi_internal_fw_ioctl_event {
|
|||
/* payload max size is WMI_MAX_IOCTL_REPLY_PAYLOAD_SIZE
|
||||
* Must be the last member of the struct
|
||||
*/
|
||||
__le32 payload[0];
|
||||
__le32 payload[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_INTERNAL_FW_EVENT_EVENTID */
|
||||
|
@ -1788,7 +1788,7 @@ struct wmi_internal_fw_event_event {
|
|||
/* payload max size is WMI_MAX_INTERNAL_EVENT_PAYLOAD_SIZE
|
||||
* Must be the last member of the struct
|
||||
*/
|
||||
__le32 payload[0];
|
||||
__le32 payload[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_SET_VRING_PRIORITY_WEIGHT_CMDID */
|
||||
|
@ -1818,7 +1818,7 @@ struct wmi_set_vring_priority_cmd {
|
|||
*/
|
||||
u8 num_of_vrings;
|
||||
u8 reserved[3];
|
||||
struct wmi_vring_priority vring_priority[0];
|
||||
struct wmi_vring_priority vring_priority[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_BF_CONTROL_CMDID - deprecated */
|
||||
|
@ -1910,7 +1910,7 @@ struct wmi_bf_control_ex_cmd {
|
|||
u8 each_mcs_cfg_size;
|
||||
u8 reserved1;
|
||||
/* Configuration for each MCS */
|
||||
struct wmi_bf_control_ex_mcs each_mcs_cfg[0];
|
||||
struct wmi_bf_control_ex_mcs each_mcs_cfg[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_LINK_STATS_CMD */
|
||||
|
@ -2192,7 +2192,7 @@ struct wmi_fw_ver_event {
|
|||
/* FW capabilities info
|
||||
* Must be the last member of the struct
|
||||
*/
|
||||
__le32 fw_capabilities[0];
|
||||
__le32 fw_capabilities[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_GET_RF_STATUS_EVENTID */
|
||||
|
@ -2270,7 +2270,7 @@ struct wmi_mac_addr_resp_event {
|
|||
struct wmi_eapol_rx_event {
|
||||
u8 src_mac[WMI_MAC_LEN];
|
||||
__le16 eapol_len;
|
||||
u8 eapol[0];
|
||||
u8 eapol[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_READY_EVENTID */
|
||||
|
@ -2343,7 +2343,7 @@ struct wmi_connect_event {
|
|||
u8 aid;
|
||||
u8 reserved2[2];
|
||||
/* not in use */
|
||||
u8 assoc_info[0];
|
||||
u8 assoc_info[];
|
||||
} __packed;
|
||||
|
||||
/* disconnect_reason */
|
||||
|
@ -2376,7 +2376,7 @@ struct wmi_disconnect_event {
|
|||
/* last assoc req may passed to host - not in used */
|
||||
u8 assoc_resp_len;
|
||||
/* last assoc req may passed to host - not in used */
|
||||
u8 assoc_info[0];
|
||||
u8 assoc_info[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_SCAN_COMPLETE_EVENTID */
|
||||
|
@ -2400,7 +2400,7 @@ struct wmi_ft_auth_status_event {
|
|||
u8 reserved[3];
|
||||
u8 mac_addr[WMI_MAC_LEN];
|
||||
__le16 ie_len;
|
||||
u8 ie_info[0];
|
||||
u8 ie_info[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_FT_REASSOC_STATUS_EVENTID */
|
||||
|
@ -2418,7 +2418,7 @@ struct wmi_ft_reassoc_status_event {
|
|||
__le16 reassoc_req_ie_len;
|
||||
__le16 reassoc_resp_ie_len;
|
||||
u8 reserved[4];
|
||||
u8 ie_info[0];
|
||||
u8 ie_info[];
|
||||
} __packed;
|
||||
|
||||
/* wmi_rx_mgmt_info */
|
||||
|
@ -2461,7 +2461,7 @@ struct wmi_stop_sched_scan_event {
|
|||
|
||||
struct wmi_sched_scan_result_event {
|
||||
struct wmi_rx_mgmt_info info;
|
||||
u8 payload[0];
|
||||
u8 payload[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_ACS_PASSIVE_SCAN_COMPLETE_EVENT */
|
||||
|
@ -2492,7 +2492,7 @@ struct wmi_acs_passive_scan_complete_event {
|
|||
__le16 filled;
|
||||
u8 num_scanned_channels;
|
||||
u8 reserved;
|
||||
struct scan_acs_info scan_info_list[0];
|
||||
struct scan_acs_info scan_info_list[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_BA_STATUS_EVENTID */
|
||||
|
@ -2751,7 +2751,7 @@ struct wmi_rf_xpm_read_result_event {
|
|||
u8 status;
|
||||
u8 reserved[3];
|
||||
/* requested num_bytes of data */
|
||||
u8 data_bytes[0];
|
||||
u8 data_bytes[];
|
||||
} __packed;
|
||||
|
||||
/* EVENT: WMI_RF_XPM_WRITE_RESULT_EVENTID */
|
||||
|
@ -2769,7 +2769,7 @@ struct wmi_tx_mgmt_packet_event {
|
|||
/* WMI_RX_MGMT_PACKET_EVENTID */
|
||||
struct wmi_rx_mgmt_packet_event {
|
||||
struct wmi_rx_mgmt_info info;
|
||||
u8 payload[0];
|
||||
u8 payload[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_ECHO_RSP_EVENTID */
|
||||
|
@ -2969,7 +2969,7 @@ struct wmi_rs_cfg_ex_cmd {
|
|||
u8 each_mcs_cfg_size;
|
||||
u8 reserved[3];
|
||||
/* Configuration for each MCS */
|
||||
struct wmi_rs_cfg_ex_mcs each_mcs_cfg[0];
|
||||
struct wmi_rs_cfg_ex_mcs each_mcs_cfg[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_RS_CFG_EX_EVENTID */
|
||||
|
@ -3178,7 +3178,7 @@ struct wmi_get_detailed_rs_res_ex_event {
|
|||
u8 each_mcs_results_size;
|
||||
u8 reserved1[3];
|
||||
/* Results for each MCS */
|
||||
struct wmi_rs_results_ex_mcs each_mcs_results[0];
|
||||
struct wmi_rs_results_ex_mcs each_mcs_results[];
|
||||
} __packed;
|
||||
|
||||
/* BRP antenna limit mode */
|
||||
|
@ -3320,7 +3320,7 @@ struct wmi_set_link_monitor_cmd {
|
|||
u8 rssi_hyst;
|
||||
u8 reserved[12];
|
||||
u8 rssi_thresholds_list_size;
|
||||
s8 rssi_thresholds_list[0];
|
||||
s8 rssi_thresholds_list[];
|
||||
} __packed;
|
||||
|
||||
/* wmi_link_monitor_event_type */
|
||||
|
@ -3637,7 +3637,7 @@ struct wmi_tof_ftm_per_dest_res_event {
|
|||
/* Measurments are from RFs, defined by the mask */
|
||||
__le32 meas_rf_mask;
|
||||
u8 reserved0[3];
|
||||
struct wmi_responder_ftm_res responder_ftm_res[0];
|
||||
struct wmi_responder_ftm_res responder_ftm_res[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_TOF_CFG_RESPONDER_EVENTID */
|
||||
|
@ -3669,7 +3669,7 @@ struct wmi_tof_channel_info_event {
|
|||
/* data report length */
|
||||
u8 len;
|
||||
/* data report payload */
|
||||
u8 report[0];
|
||||
u8 report[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_TOF_SET_TX_RX_OFFSET_EVENTID */
|
||||
|
@ -4085,7 +4085,7 @@ struct wmi_link_stats_event {
|
|||
u8 has_next;
|
||||
u8 reserved[5];
|
||||
/* a stream of wmi_link_stats_record_s */
|
||||
u8 payload[0];
|
||||
u8 payload[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_LINK_STATS_EVENT */
|
||||
|
@ -4094,7 +4094,7 @@ struct wmi_link_stats_record {
|
|||
u8 record_type_id;
|
||||
u8 reserved;
|
||||
__le16 record_size;
|
||||
u8 record[0];
|
||||
u8 record[];
|
||||
} __packed;
|
||||
|
||||
/* WMI_LINK_STATS_TYPE_BASIC */
|
||||
|
|
Loading…
Reference in New Issue