irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility
Make sure that constants which are supposed to be applied on 64-bit data is actually unsigned long long, so they won't be truncated when used in 32-bit mode. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -196,7 +196,7 @@ typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
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static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
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{
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cmd->raw_cmd[0] &= ~0xffUL;
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cmd->raw_cmd[0] &= ~0xffULL;
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cmd->raw_cmd[0] |= cmd_nr;
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}
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@ -208,43 +208,43 @@ static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
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static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
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{
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cmd->raw_cmd[1] &= ~0xffffffffUL;
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cmd->raw_cmd[1] &= ~0xffffffffULL;
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cmd->raw_cmd[1] |= id;
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}
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static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
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{
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cmd->raw_cmd[1] &= 0xffffffffUL;
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cmd->raw_cmd[1] &= 0xffffffffULL;
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cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
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}
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static void its_encode_size(struct its_cmd_block *cmd, u8 size)
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{
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cmd->raw_cmd[1] &= ~0x1fUL;
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cmd->raw_cmd[1] &= ~0x1fULL;
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cmd->raw_cmd[1] |= size & 0x1f;
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}
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static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
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{
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cmd->raw_cmd[2] &= ~0xffffffffffffUL;
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cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
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cmd->raw_cmd[2] &= ~0xffffffffffffULL;
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cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00ULL;
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}
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static void its_encode_valid(struct its_cmd_block *cmd, int valid)
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{
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cmd->raw_cmd[2] &= ~(1UL << 63);
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cmd->raw_cmd[2] &= ~(1ULL << 63);
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cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
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}
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static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
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{
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cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
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cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
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cmd->raw_cmd[2] &= ~(0xffffffffULL << 16);
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cmd->raw_cmd[2] |= (target_addr & (0xffffffffULL << 16));
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}
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static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
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{
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cmd->raw_cmd[2] &= ~0xffffUL;
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cmd->raw_cmd[2] &= ~0xffffULL;
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cmd->raw_cmd[2] |= col;
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}
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@ -657,8 +657,8 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
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its = its_dev->its;
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addr = its->phys_base + GITS_TRANSLATER;
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msg->address_lo = addr & ((1UL << 32) - 1);
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msg->address_hi = addr >> 32;
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msg->address_lo = lower_32_bits(addr);
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msg->address_hi = upper_32_bits(addr);
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msg->data = its_get_event_id(d);
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iommu_dma_map_msi_msg(d->irq, msg);
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@ -935,9 +935,9 @@ retry_baser:
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}
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if (val != tmp) {
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pr_err("ITS@%pa: %s doesn't stick: %lx %lx\n",
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pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
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&its->phys_base, its_base_type_string[type],
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(unsigned long) val, (unsigned long) tmp);
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val, tmp);
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free_pages((unsigned long)base, order);
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return -ENXIO;
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}
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@ -239,7 +239,7 @@
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#define GITS_TYPER_PTA (1UL << 19)
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#define GITS_TYPER_HWCOLLCNT_SHIFT 24
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#define GITS_CBASER_VALID (1UL << 63)
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#define GITS_CBASER_VALID (1ULL << 63)
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#define GITS_CBASER_SHAREABILITY_SHIFT (10)
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#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
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#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
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@ -265,7 +265,7 @@
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#define GITS_BASER_NR_REGS 8
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#define GITS_BASER_VALID (1UL << 63)
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#define GITS_BASER_VALID (1ULL << 63)
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#define GITS_BASER_INDIRECT (1ULL << 62)
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#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
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