ASoC: max98090: Add master clock handling
If master clock is provided through device tree, then update the master clock frequency during set_sysclk. Documentation has been updated to reflect the change. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
parent
2c81a10ae6
commit
b10ab7b838
|
@ -10,6 +10,12 @@ Required properties:
|
|||
|
||||
- interrupts : The CODEC's interrupt output.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks: The phandle of the master clock to the CODEC
|
||||
|
||||
- clock-names: Should be "mclk"
|
||||
|
||||
Pins on the device (for linking into audio routes):
|
||||
|
||||
* MIC1
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/clk.h>
|
||||
#include <sound/jack.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
|
@ -1798,6 +1799,19 @@ static int max98090_set_bias_level(struct snd_soc_codec *codec,
|
|||
break;
|
||||
|
||||
case SND_SOC_BIAS_PREPARE:
|
||||
/*
|
||||
* SND_SOC_BIAS_PREPARE is called while preparing for a
|
||||
* transition to ON or away from ON. If current bias_level
|
||||
* is SND_SOC_BIAS_ON, then it is preparing for a transition
|
||||
* away from ON. Disable the clock in that case, otherwise
|
||||
* enable it.
|
||||
*/
|
||||
if (!IS_ERR(max98090->mclk)) {
|
||||
if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
|
||||
clk_disable_unprepare(max98090->mclk);
|
||||
else
|
||||
clk_prepare_enable(max98090->mclk);
|
||||
}
|
||||
break;
|
||||
|
||||
case SND_SOC_BIAS_STANDBY:
|
||||
|
@ -1927,6 +1941,11 @@ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
|
|||
if (freq == max98090->sysclk)
|
||||
return 0;
|
||||
|
||||
if (!IS_ERR(max98090->mclk)) {
|
||||
freq = clk_round_rate(max98090->mclk, freq);
|
||||
clk_set_rate(max98090->mclk, freq);
|
||||
}
|
||||
|
||||
/* Setup clocks for slave mode, and using the PLL
|
||||
* PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
|
||||
* 0x02 (when master clk is 20MHz to 40MHz)..
|
||||
|
@ -2211,6 +2230,10 @@ static int max98090_probe(struct snd_soc_codec *codec)
|
|||
|
||||
dev_dbg(codec->dev, "max98090_probe\n");
|
||||
|
||||
max98090->mclk = devm_clk_get(codec->dev, "mclk");
|
||||
if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
max98090->codec = codec;
|
||||
|
||||
/* Reset the codec, the DSP core, and disable all interrupts */
|
||||
|
|
|
@ -1524,6 +1524,7 @@ struct max98090_priv {
|
|||
struct snd_soc_codec *codec;
|
||||
enum max98090_type devtype;
|
||||
struct max98090_pdata *pdata;
|
||||
struct clk *mclk;
|
||||
unsigned int sysclk;
|
||||
unsigned int bclk;
|
||||
unsigned int lrclk;
|
||||
|
|
Loading…
Reference in New Issue