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spi: xtensa-xtfpga: fix register endianness 

XTFPGA SPI controller has native endian registers.
Fix register acessors so that they work in big-endian configurations.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
This commit is contained in:
Max Filippov 2015-09-22 14:32:03 +03:00 committed by Mark Brown
parent 6ff33f3902
commit b0b4855099
1 changed files with 2 additions and 2 deletions
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4
drivers/spi/spi-xtensa-xtfpga.c
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@ -34,13 +34,13 @@ struct xtfpga_spi {
static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi,
unsigned addr, u32 val)
{
iowrite32(val, spi->regs + addr);
__raw_writel(val, spi->regs + addr);
}
static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
unsigned addr)
{
return ioread32(spi->regs + addr);
return __raw_readl(spi->regs + addr);
}
static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)