drm/amd/display: Query VCO frequency from register for DCN3.1
[Why] Hardcoding the VCO frequency isn't correct since we don't own or control the value. In the case where the hardcode is also missing we can't lightup display. [How] Query from the CLK register instead. Update the DFS frequency to be able to compute the VCO frequency. Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas
Alex Deucher
parent
f30f551587
commit
b0364fa4fc
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@ -48,6 +48,21 @@
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#include "dc_dmub_srv.h"
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#include "yellow_carp_offset.h"
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#define regCLK1_CLK_PLL_REQ 0x0237
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#define regCLK1_CLK_PLL_REQ_BASE_IDX 0
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#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
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#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
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#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
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#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
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#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
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#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
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#define REG(reg_name) \
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(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
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#define TO_CLK_MGR_DCN31(clk_mgr)\
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container_of(clk_mgr, struct clk_mgr_dcn31, base)
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@ -229,7 +244,32 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
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static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
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{
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return 0;
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/* get FbMult value */
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struct fixed31_32 pll_req;
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unsigned int fbmult_frac_val = 0;
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unsigned int fbmult_int_val = 0;
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/*
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* Register value of fbmult is in 8.16 format, we are converting to 31.32
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* to leverage the fix point operations available in driver
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*/
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REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
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REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
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pll_req = dc_fixpt_from_int(fbmult_int_val);
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/*
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* since fractional part is only 16 bit in register definition but is 32 bit
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* in our fix point definiton, need to shift left by 16 to obtain correct value
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*/
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pll_req.value |= fbmult_frac_val << 16;
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/* multiply by REFCLK period */
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pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
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/* integer part is now VCO frequency in kHz */
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return dc_fixpt_floor(pll_req);
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}
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static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
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@ -592,6 +632,7 @@ void dcn31_clk_mgr_construct(
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clk_mgr->base.dprefclk_ss_percentage = 0;
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clk_mgr->base.dprefclk_ss_divider = 1000;
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clk_mgr->base.ss_on_dprefclk = false;
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clk_mgr->base.dfs_ref_freq_khz = 48000;
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clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
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clk_mgr->base.base.ctx,
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@ -27,60 +27,6 @@
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#define __DCN31_CLK_MGR_H__
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#include "clk_mgr_internal.h"
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//CLK1_CLK_PLL_REQ
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#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
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#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
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#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
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#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
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#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
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#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
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#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
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//CLK1_CLK0_DFS_CNTL
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#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0
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#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL
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/*DPREF clock related*/
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#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
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#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
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#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
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#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
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#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
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#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
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#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
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#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
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//CLK3_0_CLK3_CLK_PLL_REQ
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#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
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#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
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#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
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#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
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#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
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#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
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#define mmCLK0_CLK3_DFS_CNTL 0x16C60
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#define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60
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#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60
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#define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060
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#define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260
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#define mmCLK0_CLK_PLL_REQ 0x16C10
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#define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10
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#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10
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#define mmCLK02_CLK0_CLK_PLL_REQ 0x17010
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#define mmCLK03_CLK0_CLK_PLL_REQ 0x17210
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#define mmCLK1_CLK_PLL_REQ 0x1B00D
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#define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D
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#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
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#define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D
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#define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D
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#define mmCLK2_CLK_PLL_REQ 0x17E0D
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/*AMCLK*/
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#define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F
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#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
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#endif
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struct dcn31_watermarks;
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struct dcn31_smu_watermark_set {
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