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pinctrl: sh-pfc: r8a7796: Add support for INTC-EX IRQ pins 

Most pins on the r8a7796 SoC can be configured in GPIO mode for
interrupt and GPIO functionality, while a couple of them can also
be routed to the INTC-EX hardware block (formerly known as IRQC).

On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
this patch adds support for them to the PFC driver as "intc_ex_irqN".

[takeshi.kihara.df: Ported from commit bb46f6f3f3 ("pinctrl: sh-pfc:
 r8a7795: Add support for INTC-EX IRQ pins")
 to drivers/pinctrl/sh-pfc/pfc-r8a7796.c]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Takeshi Kihara 2016-10-24 20:40:09 +09:00 committed by Geert Uytterhoeven
parent 8480e6ca80
commit b014912f6c
1 changed files with 60 additions and 0 deletions
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60
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
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@ -2392,6 +2392,50 @@ static const unsigned int i2c6_c_mux[] = {
SDA6_C_MARK, SCL6_C_MARK,
};
/* - INTC-EX ---------------------------------------------------------------- */
static const unsigned int intc_ex_irq0_pins[] = {
/* IRQ0 */
RCAR_GP_PIN(2, 0),
};
static const unsigned int intc_ex_irq0_mux[] = {
IRQ0_MARK,
};
static const unsigned int intc_ex_irq1_pins[] = {
/* IRQ1 */
RCAR_GP_PIN(2, 1),
};
static const unsigned int intc_ex_irq1_mux[] = {
IRQ1_MARK,
};
static const unsigned int intc_ex_irq2_pins[] = {
/* IRQ2 */
RCAR_GP_PIN(2, 2),
};
static const unsigned int intc_ex_irq2_mux[] = {
IRQ2_MARK,
};
static const unsigned int intc_ex_irq3_pins[] = {
/* IRQ3 */
RCAR_GP_PIN(2, 3),
};
static const unsigned int intc_ex_irq3_mux[] = {
IRQ3_MARK,
};
static const unsigned int intc_ex_irq4_pins[] = {
/* IRQ4 */
RCAR_GP_PIN(2, 4),
};
static const unsigned int intc_ex_irq4_mux[] = {
IRQ4_MARK,
};
static const unsigned int intc_ex_irq5_pins[] = {
/* IRQ5 */
RCAR_GP_PIN(2, 5),
};
static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* SCK */
@ -3922,6 +3966,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c6_a),
SH_PFC_PIN_GROUP(i2c6_b),
SH_PFC_PIN_GROUP(i2c6_c),
SH_PFC_PIN_GROUP(intc_ex_irq0),
SH_PFC_PIN_GROUP(intc_ex_irq1),
SH_PFC_PIN_GROUP(intc_ex_irq2),
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
@ -4286,6 +4336,15 @@ static const char * const i2c6_groups[] = {
"i2c6_c",
};
static const char * const intc_ex_groups[] = {
"intc_ex_irq0",
"intc_ex_irq1",
"intc_ex_irq2",
"intc_ex_irq3",
"intc_ex_irq4",
"intc_ex_irq5",
};
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
@ -4580,6 +4639,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c6),
SH_PFC_FUNCTION(intc_ex),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),