drm/amd/display: Revert dram_clock_change_latency for DCN2.1
[WHY & HOW] Using values provided by DF for latency may cause hangs in multi display configurations. Revert change to previous value. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Haonan Wang <Haonan.Wang2@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -296,7 +296,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
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.num_banks = 8,
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.num_chans = 4,
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.vmm_page_size_bytes = 4096,
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.dram_clock_change_latency_us = 11.72,
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.dram_clock_change_latency_us = 23.84,
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.return_bus_width_bytes = 64,
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.dispclk_dppclk_vco_speed_mhz = 3600,
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.xfc_bus_transport_time_us = 4,
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