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clk: spear: Remove CLK_IS_ROOT 

This flag is a no-op now. Remove usage of the flag.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Stephen Boyd 2016-03-01 11:00:00 -08:00
parent 728f288d2a
commit afb4bdc9d8
4 changed files with 19 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/clk/spear/spear1310_clock.c
View File

@ -386,24 +386,20 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
{ {
struct clk *clk, *clk1; struct clk *clk, *clk1;
clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
32000);
clk_register_clkdev(clk, "osc_32k_clk", NULL); clk_register_clkdev(clk, "osc_32k_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
24000000);
clk_register_clkdev(clk, "osc_24m_clk", NULL); clk_register_clkdev(clk, "osc_24m_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
25000000);
clk_register_clkdev(clk, "osc_25m_clk", NULL); clk_register_clkdev(clk, "osc_25m_clk", NULL);
clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
125000000);
clk_register_clkdev(clk, "gmii_pad_clk", NULL); clk_register_clkdev(clk, "gmii_pad_clk", NULL);
clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
CLK_IS_ROOT, 12288000); 12288000);
clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
/* clock derived from 32 KHz osc clk */ /* clock derived from 32 KHz osc clk */
@ -897,11 +893,10 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
&_lock); &_lock);
clk_register_clkdev(clk, "ras_apb_clk", NULL); clk_register_clkdev(clk, "ras_apb_clk", NULL);
clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, 0,
50000000); 50000000);
clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, 0, 50000000);
50000000);
clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0, SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,

16
drivers/clk/spear/spear1340_clock.c
View File

@ -443,24 +443,20 @@ void __init spear1340_clk_init(void __iomem *misc_base)
{ {
struct clk *clk, *clk1; struct clk *clk, *clk1;
clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
32000);
clk_register_clkdev(clk, "osc_32k_clk", NULL); clk_register_clkdev(clk, "osc_32k_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
24000000);
clk_register_clkdev(clk, "osc_24m_clk", NULL); clk_register_clkdev(clk, "osc_24m_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
25000000);
clk_register_clkdev(clk, "osc_25m_clk", NULL); clk_register_clkdev(clk, "osc_25m_clk", NULL);
clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
125000000);
clk_register_clkdev(clk, "gmii_pad_clk", NULL); clk_register_clkdev(clk, "gmii_pad_clk", NULL);
clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
CLK_IS_ROOT, 12288000); 12288000);
clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
/* clock derived from 32 KHz osc clk */ /* clock derived from 32 KHz osc clk */

8
drivers/clk/spear/spear3xx_clock.c
View File

@ -251,7 +251,7 @@ static void __init spear320_clk_init(void __iomem *soc_config_base,
struct clk *clk; struct clk *clk;
clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
CLK_IS_ROOT, 125000000); 0, 125000000);
clk_register_clkdev(clk, "smii_125m_pad", NULL); clk_register_clkdev(clk, "smii_125m_pad", NULL);
clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
@ -391,12 +391,10 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
{ {
struct clk *clk, *clk1, *ras_apb_clk; struct clk *clk, *clk1, *ras_apb_clk;
clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
32000);
clk_register_clkdev(clk, "osc_32k_clk", NULL); clk_register_clkdev(clk, "osc_32k_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
24000000);
clk_register_clkdev(clk, "osc_24m_clk", NULL); clk_register_clkdev(clk, "osc_24m_clk", NULL);
/* clock derived from 32 KHz osc clk */ /* clock derived from 32 KHz osc clk */

6
drivers/clk/spear/spear6xx_clock.c
View File

@ -117,12 +117,10 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
{ {
struct clk *clk, *clk1; struct clk *clk, *clk1;
clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
32000);
clk_register_clkdev(clk, "osc_32k_clk", NULL); clk_register_clkdev(clk, "osc_32k_clk", NULL);
clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT, clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000);
30000000);
clk_register_clkdev(clk, "osc_30m_clk", NULL); clk_register_clkdev(clk, "osc_30m_clk", NULL);
/* clock derived from 32 KHz osc clk */ /* clock derived from 32 KHz osc clk */