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drm/amdgpu: Use less generic enum definitions 

alpha:allmodconfig fails to build as follows.

drivers/gpu/drm/amd/amdgpu/amdgpu.h:1006:2: error:
	expected identifier before '(' token
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1011:28: error:
	'NGG_BUF_MAX' undeclared here

The problem is not really the enum definition of NGG_BUF_MAX but PARAM,
which happens to be defined differently for alpha and a couple of other
architectures.

Use less generic defines for NGG enums to solve the problem.

Fixes: bce23e00f3 ("drm/amdgpu: add NGG parameters")
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Guenter Roeck 2017-05-03 23:49:18 -07:00 committed by Alex Deucher
parent ad7d0ff3e7
commit af8baf1518
3 changed files with 26 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -1004,10 +1004,10 @@ struct amdgpu_ngg_buf {
};
enum {
PRIM = 0,
POS,
CNTL,
PARAM,
NGG_PRIM = 0,
NGG_POS,
NGG_CNTL,
NGG_PARAM,
NGG_BUF_MAX
};

16
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View File

@ -545,14 +545,14 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
adev->gfx.config.double_offchip_lds_buf;
if (amdgpu_ngg) {
dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[PRIM].gpu_addr;
dev_info.prim_buf_size = adev->gfx.ngg.buf[PRIM].size;
dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[POS].gpu_addr;
dev_info.pos_buf_size = adev->gfx.ngg.buf[POS].size;
dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[CNTL].gpu_addr;
dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[CNTL].size;
dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[PARAM].gpu_addr;
dev_info.param_buf_size = adev->gfx.ngg.buf[PARAM].size;
dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
}
dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;

28
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -890,7 +890,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
/* Primitive Buffer */
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PRIM],
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
amdgpu_prim_buf_per_se,
64 * 1024);
if (r) {
@ -899,7 +899,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
}
/* Position Buffer */
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[POS],
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
amdgpu_pos_buf_per_se,
256 * 1024);
if (r) {
@ -908,7 +908,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
}
/* Control Sideband */
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[CNTL],
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
amdgpu_cntl_sb_buf_per_se,
256);
if (r) {
@ -920,7 +920,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
if (amdgpu_param_buf_per_se <= 0)
goto out;
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PARAM],
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
amdgpu_param_buf_per_se,
512 * 1024);
if (r) {
@ -949,45 +949,45 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
/* Program buffer size */
data = 0;
size = adev->gfx.ngg.buf[PRIM].size / 256;
size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
size = adev->gfx.ngg.buf[POS].size / 256;
size = adev->gfx.ngg.buf[NGG_POS].size / 256;
data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
data = 0;
size = adev->gfx.ngg.buf[CNTL].size / 256;
size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
size = adev->gfx.ngg.buf[PARAM].size / 1024;
size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
/* Program buffer base address */
base = lower_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
base = upper_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr);
base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
base = lower_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
base = upper_32_bits(adev->gfx.ngg.buf[POS].gpu_addr);
base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
base = lower_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
base = upper_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr);
base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);