sparc/PCI: Add mem64 resource parsing for root bus
David reported that a T5-8 sparc system failed to boot with:
pci_sun4v f02dbcfc: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0x804000000000-0x80400fffffff] (bus address [0x0000-0xfffffff])
pci_bus 0000:00: root bus resource [mem 0x800000000000-0x80007effffff] (bus address [0x00000000-0x7effffff])
pci 0000:00:01.0: can't claim BAR 15 [mem 0x100000000-0x4afffffff pref]: no compatible bridge window
Note that we don't know about a host bridge aperture that contains
BAR 15. OF does report a MEM64 aperture, but before this patch,
pci_determine_mem_io_space() ignored it.
Add support for host bridge apertures with 64-bit PCI addresses. Also
set IORESOURCE_MEM_64 for PCI device and bridge resources in PCI 64-bit
memory space.
Sparc doesn't actually print the device and bridge resources, but after
this patch, we should have the equivalent of this:
pci_sun4v f02dbcfc: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0x804000000000-0x80400fffffff] (bus address [0x0000-0xfffffff])
pci_bus 0000:00: root bus resource [mem 0x800000000000-0x80007effffff] (bus address [0x00000000-0x7effffff])
pci_bus 0000:00: root bus resource [mem 0x800100000000-0x8007ffffffff] (bus address [0x100000000-0x7ffffffff])
pci 0000:00:01.0: bridge window [mem 0x800100000000-0x8004afffffff 64bit pref]
[bhelgaas: changelog, URL to David's report]
Fixes: d63e2e1f3d
("sparc/PCI: Clip bridge windows to fit in upstream windows")
Link: http://lkml.kernel.org/r/5514391F.2030300@oracle.com
Reported-by: David Ahern <david.ahern@oracle.com>
Tested-by: David Ahern <david.ahern@oracle.com>
Tested-by: Khalid Aziz <khalid.aziz@oracle.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
parent
597becb4ad
commit
af86fa4001
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@ -185,8 +185,10 @@ static unsigned long pci_parse_of_flags(u32 addr0)
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if (addr0 & 0x02000000) {
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flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
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flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
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flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
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if (addr0 & 0x01000000)
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flags |= IORESOURCE_MEM_64
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| PCI_BASE_ADDRESS_MEM_TYPE_64;
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if (addr0 & 0x40000000)
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flags |= IORESOURCE_PREFETCH
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| PCI_BASE_ADDRESS_MEM_PREFETCH;
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@ -655,6 +657,9 @@ struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
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pbm->io_space.start);
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pci_add_resource_offset(&resources, &pbm->mem_space,
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pbm->mem_space.start);
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if (pbm->mem64_space.flags)
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pci_add_resource_offset(&resources, &pbm->mem64_space,
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pbm->mem_space.start);
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pbm->busn.start = pbm->pci_first_busno;
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pbm->busn.end = pbm->pci_last_busno;
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pbm->busn.flags = IORESOURCE_BUS;
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@ -406,6 +406,7 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
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}
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num_pbm_ranges = i / sizeof(*pbm_ranges);
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memset(&pbm->mem64_space, 0, sizeof(struct resource));
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for (i = 0; i < num_pbm_ranges; i++) {
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const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
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@ -451,7 +452,12 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
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break;
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case 3:
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/* XXX 64-bit MEM handling XXX */
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/* 64-bit MEM handling */
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pbm->mem64_space.start = a;
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pbm->mem64_space.end = a + size - 1UL;
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pbm->mem64_space.flags = IORESOURCE_MEM;
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saw_mem = 1;
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break;
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default:
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break;
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@ -465,15 +471,22 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
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prom_halt();
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}
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printk("%s: PCI IO[%llx] MEM[%llx]\n",
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printk("%s: PCI IO[%llx] MEM[%llx]",
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pbm->name,
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pbm->io_space.start,
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pbm->mem_space.start);
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if (pbm->mem64_space.flags)
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printk(" MEM64[%llx]",
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pbm->mem64_space.start);
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printk("\n");
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pbm->io_space.name = pbm->mem_space.name = pbm->name;
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pbm->mem64_space.name = pbm->name;
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request_resource(&ioport_resource, &pbm->io_space);
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request_resource(&iomem_resource, &pbm->mem_space);
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if (pbm->mem64_space.flags)
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request_resource(&iomem_resource, &pbm->mem64_space);
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pci_register_legacy_regions(&pbm->io_space,
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&pbm->mem_space);
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@ -97,6 +97,7 @@ struct pci_pbm_info {
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/* PBM I/O and Memory space resources. */
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struct resource io_space;
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struct resource mem_space;
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struct resource mem64_space;
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struct resource busn;
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/* Base of PCI Config space, can be per-PBM or shared. */
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