ARM: oxnas: Add OX820 SMP support
The Oxford Semiconductor OX820 is a ARM11MPcore based SoC sharing some features with the OX810 earlier SoC. This patch adds the core to wake up the second core. Clarifications about Copyrights dates : - hotplug.c was taken from an old versatile code by Ma Haijun and left verbatim - headsmp.S was taken from an old versatile code and adapted by Ma Haijun - platsmp.c is a mix from versatile code, Ma Haijun code and my code for DT Hence the 2002/2003 ARM Coryrights and 2013 Ma Haijun Copyrights. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Neil Armstrong
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@ -0,0 +1,2 @@
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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/*
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* Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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__INIT
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/*
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* OX820 specific entry point for secondary CPUs.
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*/
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ENTRY(ox820_secondary_startup)
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mov r4, #0
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/* invalidate both caches and branch target cache */
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mcr p15, 0, r4, c7, c7, 0
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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@ -0,0 +1,109 @@
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/*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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static inline void cpu_enter_lowpower(void)
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{
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unsigned int v;
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asm volatile(
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" mcr p15, 0, %1, c7, c5, 0\n"
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" mcr p15, 0, %1, c7, c10, 4\n"
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/*
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* Turn off coherency
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*/
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" mrc p15, 0, %0, c1, c0, 1\n"
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" bic %0, %0, #0x20\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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" mrc p15, 0, %0, c1, c0, 0\n"
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" bic %0, %0, %2\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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: "=&r" (v)
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: "r" (0), "Ir" (CR_C)
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: "cc");
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}
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static inline void cpu_leave_lowpower(void)
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{
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unsigned int v;
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asm volatile( "mrc p15, 0, %0, c1, c0, 0\n"
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" orr %0, %0, %1\n"
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" mcr p15, 0, %0, c1, c0, 0\n"
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" mrc p15, 0, %0, c1, c0, 1\n"
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" orr %0, %0, #0x20\n"
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" mcr p15, 0, %0, c1, c0, 1\n"
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: "=&r" (v)
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: "Ir" (CR_C)
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: "cc");
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}
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static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
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{
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/*
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* there is no power-control hardware on this platform, so all
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* we can do is put the core into WFI; this is safe as the calling
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* code will have already disabled interrupts
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*/
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for (;;) {
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/*
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* here's the WFI
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*/
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asm(".word 0xe320f003\n"
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:
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:
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: "memory", "cc");
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if (pen_release == cpu_logical_map(cpu)) {
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/*
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* OK, proper wakeup, we're done
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*/
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break;
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}
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/*
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* Getting here, means that we have come out of WFI without
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* having been woken up - this shouldn't happen
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*
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* Just note it happening - when we're woken, we can report
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* its occurrence.
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*/
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(*spurious)++;
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}
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}
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/*
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* platform-specific code to shutdown a CPU
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*
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* Called with IRQs disabled
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*/
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void ox820_cpu_die(unsigned int cpu)
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{
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int spurious = 0;
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/*
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* we're ready for shutdown now, so do it
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*/
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cpu_enter_lowpower();
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platform_do_lowpower(cpu, &spurious);
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/*
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* bring this CPU back into the world of cache
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* coherency, and then restore interrupts
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*/
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cpu_leave_lowpower();
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if (spurious)
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pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
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}
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@ -0,0 +1,102 @@
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/*
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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extern void ox820_secondary_startup(void);
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extern void ox820_cpu_die(unsigned int cpu);
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static void __iomem *cpu_ctrl;
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static void __iomem *gic_cpu_ctrl;
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#define HOLDINGPEN_CPU_OFFSET 0xc8
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#define HOLDINGPEN_LOCATION_OFFSET 0xc4
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#define GIC_NCPU_OFFSET(cpu) (0x100 + (cpu)*0x100)
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#define GIC_CPU_CTRL 0x00
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#define GIC_CPU_CTRL_ENABLE 1
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int __init ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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/*
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* Write the address of secondary startup into the
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* system-wide flags register. The BootMonitor waits
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*/
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writel(virt_to_phys(ox820_secondary_startup),
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cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
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writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
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/*
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* Enable GIC cpu interface in CPU Interface Control Register
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*/
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writel(GIC_CPU_CTRL_ENABLE,
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gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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void __iomem *scu_base;
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np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
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scu_base = of_iomap(np, 0);
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of_node_put(np);
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if (!scu_base)
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return;
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/* Remap CPU Interrupt Interface Registers */
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np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
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gic_cpu_ctrl = of_iomap(np, 1);
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of_node_put(np);
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if (!gic_cpu_ctrl)
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goto unmap_scu;
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np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
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cpu_ctrl = of_iomap(np, 0);
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of_node_put(np);
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if (!cpu_ctrl)
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goto unmap_scu;
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scu_enable(scu_base);
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flush_cache_all();
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unmap_scu:
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iounmap(scu_base);
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}
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static const struct smp_operations ox820_smp_ops __initconst = {
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.smp_prepare_cpus = ox820_smp_prepare_cpus,
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.smp_boot_secondary = ox820_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = ox820_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);
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