From f2ce701495683936d349ab905feba74c7b572c93 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 20 May 2015 15:32:44 +0200 Subject: [PATCH 01/13] arm64: dts: mt8173: Add clock controller device nodes This adds the device nodes providing clocks on the Mediatek MT8173. These are: topckgen, infracfg, pericfg and apmixedsys. These are fed by two oscillators also added by this patch. Signed-off-by: Sascha Hauer Reviewed-by: Daniel Kurtz Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 52 +++++++++++++++++++++--- 1 file changed, 47 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 27237a1c1a87..30b2fdfc8210 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include #include #include #include "mt8173-pinfunc.h" @@ -87,6 +88,20 @@ #clock-cells = <0>; }; + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; @@ -106,11 +121,32 @@ compatible = "simple-bus"; ranges; - /* - * Pinctrl access register at 0x10005000 through regmap. - * Register 0x1000b000 is used by EINT. - */ - pio: pinctrl@10005000 { + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt8173-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: power-controller@10001000 { + compatible = "mediatek,mt8173-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: power-controller@10003000 { + compatible = "mediatek,mt8173-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@0x10005000 { compatible = "mediatek,mt8173-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; @@ -138,6 +174,12 @@ reg = <0 0x10200620 0 0x20>; }; + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt8173-apmixedsys"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + gic: interrupt-controller@10220000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From 0e84faa163c8ad42fec05d26907af8079d418bfc Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 20 May 2015 15:32:45 +0200 Subject: [PATCH 02/13] arm64: dts: mt8173: Use real clock for UARTs We used to use a fixed rate clock for the UARTs. Now that we have clock support we can associate the correct clocks to the UARTs and drop the 26MHz fixed rate UART clock. Signed-off-by: Sascha Hauer Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 30b2fdfc8210..9fbc4c190dc9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -82,12 +82,6 @@ cpu_on = <0x84000003>; }; - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - clk26m: oscillator@0 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -198,7 +192,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -207,7 +202,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -216,7 +212,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -225,7 +222,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; }; From 6cf15fc2a1aa062476c26e1895640d1c61f60a72 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 20 May 2015 15:32:46 +0200 Subject: [PATCH 03/13] arm64: dts: mt8173: Add PMIC wrapper device node This adds the device node for the PMIC wrapper. Signed-off-by: Sascha Hauer Reviewed-by: Daniel Kurtz Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 9fbc4c190dc9..ba46fe5a4a56 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include "mt8173-pinfunc.h" / { @@ -159,6 +160,17 @@ reg = <0 0x10005000 0 0x1000>; }; + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8173-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; + reset-names = "pwrap"; + clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; + clock-names = "spi", "wrap"; + }; + sysirq: intpol-controller@10200620 { compatible = "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq"; From 13421b3e8a16921dde592e3309cee15f3be1d93b Mon Sep 17 00:00:00 2001 From: Eddie Huang Date: Mon, 1 Jun 2015 21:08:26 +0800 Subject: [PATCH 04/13] arm64: dts: mt8173: Add watchdog device node Add MT8173 watchdog device node. Signed-off-by: Eddie Huang Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index ba46fe5a4a56..e880de5ec926 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -160,6 +160,12 @@ reg = <0 0x10005000 0 0x1000>; }; + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8173-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + pwrap: pwrap@1000d000 { compatible = "mediatek,mt8173-pwrap"; reg = <0 0x1000d000 0 0x1000>; From 091cf59891df5d969525d06a4da44e1a2a0e84d1 Mon Sep 17 00:00:00 2001 From: Eddie Huang Date: Wed, 17 Jun 2015 23:08:03 +0800 Subject: [PATCH 05/13] arm64: dts: mt8173: Add I2C device node Add MT8173 I2C device nodes, include I2C controllers and pins. MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5. The 6th I2C controller register base doesn't next to 5th I2C, and there is a hardware between 5th and 6th I2C controller. So SoC designer name 6th controller as "i2c6", not "i2c5". Signed-off-by: Eddie Huang Reviewed-by: Daniel Kurtz Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 147 ++++++++++++++++++++++- 1 file changed, 143 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index e880de5ec926..a9fa02b8c1b1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -153,11 +153,54 @@ interrupts = , , ; - }; - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; + i2c0_pins_a: i2c0 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c1_pins_a: i2c1 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c2_pins_a: i2c2 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c3_pins_a: i2c3 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c4_pins_a: i2c4 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c6_pins_a: i2c6 { + pins1 { + pinmux = , + ; + bias-disable; + }; + }; }; watchdog: watchdog@10007000 { @@ -244,6 +287,102 @@ clock-names = "baud", "bus"; status = "disabled"; }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11007000 0 0x70>, + <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C0>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11008000 0 0x70>, + <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11009000 0 0x70>, + <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C2>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c3@11010000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11010000 0 0x70>, + <0 0x11000280 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C3>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c4@11011000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11011000 0 0x70>, + <0 0x11000300 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C4>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c6@11013000 { + compatible = "mediatek,mt8173-i2c"; + reg = <0 0x11013000 0 0x70>, + <0 0x11000080 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C6>, + <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; From c010ff530a04ca63d120e1fad0f4268302c5e845 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 24 Jun 2015 08:17:05 +0200 Subject: [PATCH 06/13] ARM64: MediaTek MT8173: Add SCPSYS device node This adds the SCPSYS device node to the MT8173 dtsi file. Signed-off-by: Sascha Hauer Reviewed-by: Daniel Kurtz Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index a9fa02b8c1b1..0696f8fa8fc2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -203,6 +203,16 @@ }; }; + scpsys: scpsys@10006000 { + compatible = "mediatek,mt8173-scpsys"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + clocks = <&clk26m>, + <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mfg", "mm"; + infracfg = <&infracfg>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8173-wdt", "mediatek,mt6589-wdt"; From ad4df7a53a148e2e9d917e254b4e9ec9fc860ac9 Mon Sep 17 00:00:00 2001 From: Howard Chen Date: Thu, 4 Jun 2015 15:13:37 +0800 Subject: [PATCH 07/13] ARM: dts: mt8173: support arm64 cpuidle-dt This patch adds an idle-states node to describe the mt8173 idle states and also adds references to the idle-states node in all CPU nodes. Signed-off-by: Howard Chen Acked-by: Lorenzo Pieralisi Acked-by: Daniel Lezcano Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 0696f8fa8fc2..359b8b6c235a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -51,6 +51,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x000>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { @@ -58,6 +60,7 @@ compatible = "arm,cortex-a53"; reg = <0x001>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@100 { @@ -65,6 +68,7 @@ compatible = "arm,cortex-a57"; reg = <0x100>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@101 { @@ -72,6 +76,20 @@ compatible = "arm,cortex-a57"; reg = <0x101>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <639>; + exit-latency-us = <680>; + min-residency-us = <1088>; + arm,psci-suspend-param = <0x0010000>; + }; }; }; From 720570b14bb7c7494b0dbc2acc0d2065a490d31b Mon Sep 17 00:00:00 2001 From: Henry Chen Date: Fri, 3 Jul 2015 10:28:26 +0800 Subject: [PATCH 08/13] dts: mt8173-evb: Add da9211 to i2c1 Add a DA9211 dual-channel BUCK regulator to i2c1. This regulator supplies GPU and DVFS1 voltages. Signed-off-by: Henry Chen Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 30 +++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index d0ab012fa379..7f583bdea229 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -34,6 +34,36 @@ chosen { }; }; +&i2c1 { + status = "okay"; + + buck: da9211@68 { + compatible = "dlg,da9211"; + reg = <0x68>; + + regulators { + da9211_vcpu_reg: BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <4400000>; + regulator-ramp-delay = <10000>; + regulator-always-on; + }; + + da9211_vgpu_reg: BUCKB { + regulator-name = "VBUCKB"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <3000000>; + regulator-ramp-delay = <10000>; + }; + }; + }; +}; + &uart0 { status = "okay"; }; From 16ea61fc56144f1860f9edd5a219666ade01d3b8 Mon Sep 17 00:00:00 2001 From: Eddie Huang Date: Mon, 22 Jun 2015 21:19:37 +0800 Subject: [PATCH 09/13] arm64: dts: mt8173-evb: Add PMIC support The MT8173 eval board contains a MT6397 PMIC. This adds the corresponding device node to the dts file. Signed-off-by: Henry Chen Signed-off-by: Eddie Huang Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 197 ++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 7f583bdea229..986f25f0d534 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -64,6 +64,203 @@ }; }; +&pwrap { + pmic: mt6397 { + compatible = "mediatek,mt6397"; + interrupt-parent = <&pio>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + mt6397regulator: mt6397regulator { + compatible = "mediatek,mt6397-regulator"; + + mt6397_vpca15_reg: buck_vpca15 { + regulator-compatible = "buck_vpca15"; + regulator-name = "vpca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vpca7_reg: buck_vpca7 { + regulator-compatible = "buck_vpca7"; + regulator-name = "vpca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + }; + + mt6397_vsramca15_reg: buck_vsramca15 { + regulator-compatible = "buck_vsramca15"; + regulator-name = "vsramca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vsramca7_reg: buck_vsramca7 { + regulator-compatible = "buck_vsramca7"; + regulator-name = "vsramca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vcore_reg: buck_vcore { + regulator-compatible = "buck_vcore"; + regulator-name = "vcore"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vgpu_reg: buck_vgpu { + regulator-compatible = "buck_vgpu"; + regulator-name = "vgpu"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + }; + + mt6397_vdrm_reg: buck_vdrm { + regulator-compatible = "buck_vdrm"; + regulator-name = "vdrm"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vio18_reg: buck_vio18 { + regulator-compatible = "buck_vio18"; + regulator-name = "vio18"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vtcxo_reg: ldo_vtcxo { + regulator-compatible = "ldo_vtcxo"; + regulator-name = "vtcxo"; + regulator-always-on; + }; + + mt6397_va28_reg: ldo_va28 { + regulator-compatible = "ldo_va28"; + regulator-name = "va28"; + regulator-always-on; + }; + + mt6397_vcama_reg: ldo_vcama { + regulator-compatible = "ldo_vcama"; + regulator-name = "vcama"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vio28_reg: ldo_vio28 { + regulator-compatible = "ldo_vio28"; + regulator-name = "vio28"; + regulator-always-on; + }; + + mt6397_vusb_reg: ldo_vusb { + regulator-compatible = "ldo_vusb"; + regulator-name = "vusb"; + }; + + mt6397_vmc_reg: ldo_vmc { + regulator-compatible = "ldo_vmc"; + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vmch_reg: ldo_vmch { + regulator-compatible = "ldo_vmch"; + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vemc_3v3_reg: ldo_vemc3v3 { + regulator-compatible = "ldo_vemc3v3"; + regulator-name = "vemc_3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp1_reg: ldo_vgp1 { + regulator-compatible = "ldo_vgp1"; + regulator-name = "vcamd"; + regulator-min-microvolt = <1220000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + mt6397_vgp2_reg: ldo_vgp2 { + regulator-compatible = "ldo_vgp2"; + regulator-name = "vcamio"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp3_reg: ldo_vgp3 { + regulator-compatible = "ldo_vgp3"; + regulator-name = "vcamaf"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp4_reg: ldo_vgp4 { + regulator-compatible = "ldo_vgp4"; + regulator-name = "vgp4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp5_reg: ldo_vgp5 { + regulator-compatible = "ldo_vgp5"; + regulator-name = "vgp5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp6_reg: ldo_vgp6 { + regulator-compatible = "ldo_vgp6"; + regulator-name = "vgp6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vibr_reg: ldo_vibr { + regulator-compatible = "ldo_vibr"; + regulator-name = "vibr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + }; + }; +}; + &uart0 { status = "okay"; }; From c02e0e86d3043e63236d7cd2e9e4259f12ac6991 Mon Sep 17 00:00:00 2001 From: Koro Chen Date: Thu, 9 Jul 2015 11:32:05 +0800 Subject: [PATCH 10/13] arm64: dts: mt8173: Add afe device node This adds afe (audio front end) device node to the MT8173 dtsi file. Signed-off-by: Koro Chen Reviewed-by: Daniel Kurtz Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 359b8b6c235a..01033df1a149 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "mt8173-pinfunc.h" @@ -411,6 +412,37 @@ #size-cells = <0>; status = "disabled"; }; + + afe: audio-controller@11220000 { + compatible = "mediatek,mt8173-afe-pcm"; + reg = <0 0x11220000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_APLL1_DIV0>, + <&topckgen CLK_TOP_APLL2_DIV0>, + <&topckgen CLK_TOP_I2S0_M_SEL>, + <&topckgen CLK_TOP_I2S1_M_SEL>, + <&topckgen CLK_TOP_I2S2_M_SEL>, + <&topckgen CLK_TOP_I2S3_M_SEL>, + <&topckgen CLK_TOP_I2S3_B_SEL>; + clock-names = "infra_sys_audio_clk", + "top_pdn_audio", + "top_pdn_aud_intbus", + "bck0", + "bck1", + "i2s0_m", + "i2s1_m", + "i2s2_m", + "i2s3_m", + "i2s3_b"; + assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_AUD_2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_APLL2>; + }; }; }; From 9719fa5a3840b1b9de7f2c0aae57346cd6570ea7 Mon Sep 17 00:00:00 2001 From: Eddie Huang Date: Thu, 16 Jul 2015 19:36:20 +0800 Subject: [PATCH 11/13] arm64: dts: mediatek: Add MT8173 MMC dts Add node mmc0 ~ mmc3 for mt8173.dtsi Add node mmc0, mmc1 for mt8173-evb.dts Signed-off-by: Chaotian Jing Signed-off-by: Eddie Huang Reviewed-by: Daniel Kurtz Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 126 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 44 +++++++ 2 files changed, 170 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 986f25f0d534..4be66cadbc7c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -64,6 +64,132 @@ }; }; +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + vqmmc-supply = <&mt6397_vio18_reg>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + sd-uhs-sdr25; + cd-gpios = <&pio 132 0>; + vmmc-supply = <&mt6397_vmch_reg>; + vqmmc-supply = <&mt6397_vmc_reg>; +}; + +&pio { + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = ; + bias-pull-down; + }; + + pins_rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + bias-pull-down; + drive-strength = ; + }; + + pins_insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0 { + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins_rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_pins_uhs: mmc1 { + pins_cmd_dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + }; +}; + &pwrap { pmic: mt6397 { compatible = "mediatek,mt6397"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 01033df1a149..d18ee4259ee5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -443,6 +443,50 @@ assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, <&topckgen CLK_TOP_APLL2>; }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8173-mmc", + "mediatek,mt8135-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC50_0_H_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8173-mmc", + "mediatek,mt8135-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt8173-mmc", + "mediatek,mt8135-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_2>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc3: mmc@11260000 { + compatible = "mediatek,mt8173-mmc", + "mediatek,mt8135-mmc"; + reg = <0 0x11260000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_3>, + <&topckgen CLK_TOP_MSDC50_2_H_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; }; }; From afc257bc9ac9c2f9055c9f9829322b3ff7574165 Mon Sep 17 00:00:00 2001 From: Mars Cheng Date: Tue, 14 Jul 2015 14:58:12 +0800 Subject: [PATCH 12/13] Document: DT: Add bindings for mediatek MT6795 SoC Platform This adds DT binding documentation for Mediatek MT6795. Signed-off-by: Mars Cheng Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.txt | 9 +++++++-- .../devicetree/bindings/arm/mediatek/mediatek,sysirq.txt | 3 ++- Documentation/devicetree/bindings/serial/mtk-uart.txt | 5 +++-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index dd7550a29db6..ce26ff7aa9b0 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -1,12 +1,14 @@ -MediaTek mt65xx & mt81xx Platforms Device Tree Bindings +MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings -Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property: +Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the +following property: Required root node property: compatible: Must contain one of "mediatek,mt6589" "mediatek,mt6592" + "mediatek,mt6795" "mediatek,mt8127" "mediatek,mt8135" "mediatek,mt8173" @@ -20,6 +22,9 @@ Supported boards: - Evaluation board for MT6592: Required root node properties: - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; +- Evaluation board for MT6795(Helio X10): + Required root node properties: + - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; - MTK mt8127 tablet moose EVB: Required root node properties: - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt index 4f5a5352ccd8..8136b6d44871 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt @@ -1,4 +1,4 @@ -Mediatek 65xx/81xx sysirq ++Mediatek 65xx/67xx/81xx sysirq Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI interrupt. @@ -8,6 +8,7 @@ Required properties: "mediatek,mt8173-sysirq" "mediatek,mt8135-sysirq" "mediatek,mt8127-sysirq" + "mediatek,mt6795-sysirq" "mediatek,mt6592-sysirq" "mediatek,mt6589-sysirq" "mediatek,mt6582-sysirq" diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 8d63f1da07aa..5991511fa7ee 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -5,10 +5,11 @@ Required properties: * "mediatek,mt8135-uart" for MT8135 compatible UARTS * "mediatek,mt8127-uart" for MT8127 compatible UARTS * "mediatek,mt8173-uart" for MT8173 compatible UARTS + * "mediatek,mt6795-uart" for MT6795 compatible UARTS * "mediatek,mt6589-uart" for MT6589 compatible UARTS * "mediatek,mt6582-uart" for MT6582 compatible UARTS - * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582, - MT6577) + * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6795, MT6589, + MT6582, MT6577) - reg: The base address of the UART register bank. From e26945245e414eff42ee1ffeaedf198911bf1d77 Mon Sep 17 00:00:00 2001 From: Mars Cheng Date: Tue, 14 Jul 2015 14:58:13 +0800 Subject: [PATCH 13/13] arm64: dts: mediatek: add mt6795 support This adds basic chip support for MT6795 SoC Signed-off-by: Mars Cheng Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 41 +++++ arch/arm64/boot/dts/mediatek/mt6795.dtsi | 162 ++++++++++++++++++++ 3 files changed, 204 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6795-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6795.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3ce24622b231..e0a4bff2fc17 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,3 +1,4 @@ +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb always := $(dtb-y) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts new file mode 100644 index 000000000000..ad665f5835f0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "mt6795.dtsi" + +/ { + model = "MediaTek MT6795 Evaluation Board"; + compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi new file mode 100644 index 000000000000..da200e788936 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Mars.C + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/ { + compatible = "mediatek,mt6795"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x002>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x003>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + sysirq: intpol-controller@10200620 { + compatible = "mediatek,mt6795-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200620 0 0x20>; + }; + + gic: interrupt-controller@10221000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x10221000 0 0x1000>, + <0 0x10222000 0 0x2000>, + <0 0x10224000 0 0x2000>, + <0 0x10226000 0 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6795-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11005000 0 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; +};