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qlcnic: Qlogic ethernet driver for CNA devices 

o 1G/10G Ethernet Driver for Qlgic QLE8240 and QLE8242 CNA devices.

Signed-off-by: Amit Kumar Salecha <amit.salecha@qlogic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Amit Kumar Salecha 2010-01-13 00:37:25 +00:00 committed by David S. Miller
parent 6eb3a85533
commit af19b49152
8 changed files with 8728 additions and 0 deletions
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8
drivers/net/qlcnic/Makefile Normal file
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#
# Makefile for Qlogic 1G/10G Ethernet Driver for CNA devices
#
obj-$(CONFIG_QLCNIC) := qlcnic.o
qlcnic-y := qlcnic_hw.o qlcnic_main.o qlcnic_init.o \
qlcnic_ethtool.o qlcnic_ctx.o

1106
drivers/net/qlcnic/qlcnic.h Normal file
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536
drivers/net/qlcnic/qlcnic_ctx.c Normal file
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/*
* Copyright (C) 2009 - QLogic Corporation.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
* MA 02111-1307, USA.
*
* The full GNU General Public License is included in this distribution
* in the file called "COPYING".
*
*/
#include "qlcnic.h"
#define QLCHAL_VERSION 1
static u32
qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
{
u32 rsp;
int timeout = 0;
do {
/* give atleast 1ms for firmware to respond */
msleep(1);
if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
return QLCNIC_CDRP_RSP_TIMEOUT;
rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET);
} while (!QLCNIC_CDRP_IS_RSP(rsp));
return rsp;
}
static u32
qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
{
u32 rsp;
u32 signature;
u32 rcode = QLCNIC_RCODE_SUCCESS;
struct pci_dev *pdev = adapter->pdev;
signature = QLCNIC_CDRP_SIGNATURE_MAKE(pci_fn, version);
/* Acquire semaphore before accessing CRB */
if (qlcnic_api_lock(adapter))
return QLCNIC_RCODE_TIMEOUT;
QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
QLCWR32(adapter, QLCNIC_ARG1_CRB_OFFSET, arg1);
QLCWR32(adapter, QLCNIC_ARG2_CRB_OFFSET, arg2);
QLCWR32(adapter, QLCNIC_ARG3_CRB_OFFSET, arg3);
QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET, QLCNIC_CDRP_FORM_CMD(cmd));
rsp = qlcnic_poll_rsp(adapter);
if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
dev_err(&pdev->dev, "card response timeout.\n");
rcode = QLCNIC_RCODE_TIMEOUT;
} else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
rcode = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
dev_err(&pdev->dev, "failed card response code:0x%x\n",
rcode);
}
/* Release semaphore */
qlcnic_api_unlock(adapter);
return rcode;
}
int
qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
{
struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
if (recv_ctx->state == QLCNIC_HOST_CTX_STATE_ACTIVE) {
if (qlcnic_issue_cmd(adapter,
adapter->ahw.pci_func,
QLCHAL_VERSION,
recv_ctx->context_id,
mtu,
0,
QLCNIC_CDRP_CMD_SET_MTU)) {
dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
return -EIO;
}
}
return 0;
}
static int
qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
{
void *addr;
struct qlcnic_hostrq_rx_ctx *prq;
struct qlcnic_cardrsp_rx_ctx *prsp;
struct qlcnic_hostrq_rds_ring *prq_rds;
struct qlcnic_hostrq_sds_ring *prq_sds;
struct qlcnic_cardrsp_rds_ring *prsp_rds;
struct qlcnic_cardrsp_sds_ring *prsp_sds;
struct qlcnic_host_rds_ring *rds_ring;
struct qlcnic_host_sds_ring *sds_ring;
dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
u64 phys_addr;
int i, nrds_rings, nsds_rings;
size_t rq_size, rsp_size;
u32 cap, reg, val;
int err;
struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
nrds_rings = adapter->max_rds_rings;
nsds_rings = adapter->max_sds_rings;
rq_size =
SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
nsds_rings);
rsp_size =
SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
nsds_rings);
addr = pci_alloc_consistent(adapter->pdev,
rq_size, &hostrq_phys_addr);
if (addr == NULL)
return -ENOMEM;
prq = (struct qlcnic_hostrq_rx_ctx *)addr;
addr = pci_alloc_consistent(adapter->pdev,
rsp_size, &cardrsp_phys_addr);
if (addr == NULL) {
err = -ENOMEM;
goto out_free_rq;
}
prsp = (struct qlcnic_cardrsp_rx_ctx *)addr;
prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN);
cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
prq->capabilities[0] = cpu_to_le32(cap);
prq->host_int_crb_mode =
cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
prq->host_rds_crb_mode =
cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE);
prq->num_rds_rings = cpu_to_le16(nrds_rings);
prq->num_sds_rings = cpu_to_le16(nsds_rings);
prq->rds_ring_offset = cpu_to_le32(0);
val = le32_to_cpu(prq->rds_ring_offset) +
(sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
prq->sds_ring_offset = cpu_to_le32(val);
prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
le32_to_cpu(prq->rds_ring_offset));
for (i = 0; i < nrds_rings; i++) {
rds_ring = &recv_ctx->rds_rings[i];
prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
prq_rds[i].ring_kind = cpu_to_le32(i);
prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
}
prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
le32_to_cpu(prq->sds_ring_offset));
for (i = 0; i < nsds_rings; i++) {
sds_ring = &recv_ctx->sds_rings[i];
prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
prq_sds[i].msi_index = cpu_to_le16(i);
}
phys_addr = hostrq_phys_addr;
err = qlcnic_issue_cmd(adapter,
adapter->ahw.pci_func,
QLCHAL_VERSION,
(u32)(phys_addr >> 32),
(u32)(phys_addr & 0xffffffff),
rq_size,
QLCNIC_CDRP_CMD_CREATE_RX_CTX);
if (err) {
dev_err(&adapter->pdev->dev,
"Failed to create rx ctx in firmware%d\n", err);
goto out_free_rsp;
}
prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
&prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
rds_ring = &recv_ctx->rds_rings[i];
reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
rds_ring->crb_rcv_producer = qlcnic_get_ioaddr(adapter,
QLCNIC_REG(reg - 0x200));
}
prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
&prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
sds_ring = &recv_ctx->sds_rings[i];
reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
sds_ring->crb_sts_consumer = qlcnic_get_ioaddr(adapter,
QLCNIC_REG(reg - 0x200));
reg = le32_to_cpu(prsp_sds[i].interrupt_crb);
sds_ring->crb_intr_mask = qlcnic_get_ioaddr(adapter,
QLCNIC_REG(reg - 0x200));
}
recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
recv_ctx->context_id = le16_to_cpu(prsp->context_id);
recv_ctx->virt_port = prsp->virt_port;
out_free_rsp:
pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
out_free_rq:
pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
return err;
}
static void
qlcnic_fw_cmd_destroy_rx_ctx(struct qlcnic_adapter *adapter)
{
struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
if (qlcnic_issue_cmd(adapter,
adapter->ahw.pci_func,
QLCHAL_VERSION,
recv_ctx->context_id,
QLCNIC_DESTROY_CTX_RESET,
0,
QLCNIC_CDRP_CMD_DESTROY_RX_CTX)) {
dev_err(&adapter->pdev->dev,
"Failed to destroy rx ctx in firmware\n");
}
}
static int
qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter)
{
struct qlcnic_hostrq_tx_ctx *prq;
struct qlcnic_hostrq_cds_ring *prq_cds;
struct qlcnic_cardrsp_tx_ctx *prsp;
void *rq_addr, *rsp_addr;
size_t rq_size, rsp_size;
u32 temp;
int err;
u64 phys_addr;
dma_addr_t rq_phys_addr, rsp_phys_addr;
struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
rq_addr = pci_alloc_consistent(adapter->pdev,
rq_size, &rq_phys_addr);
if (!rq_addr)
return -ENOMEM;
rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
rsp_addr = pci_alloc_consistent(adapter->pdev,
rsp_size, &rsp_phys_addr);
if (!rsp_addr) {
err = -ENOMEM;
goto out_free_rq;
}
memset(rq_addr, 0, rq_size);
prq = (struct qlcnic_hostrq_tx_ctx *)rq_addr;
memset(rsp_addr, 0, rsp_size);
prsp = (struct qlcnic_cardrsp_tx_ctx *)rsp_addr;
prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
QLCNIC_CAP0_LSO);
prq->capabilities[0] = cpu_to_le32(temp);
prq->host_int_crb_mode =
cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
prq->interrupt_ctl = 0;
prq->msi_index = 0;
prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
prq_cds = &prq->cds_ring;
prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
phys_addr = rq_phys_addr;
err = qlcnic_issue_cmd(adapter,
adapter->ahw.pci_func,
QLCHAL_VERSION,
(u32)(phys_addr >> 32),
((u32)phys_addr & 0xffffffff),
rq_size,
QLCNIC_CDRP_CMD_CREATE_TX_CTX);
if (err == QLCNIC_RCODE_SUCCESS) {
temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
tx_ring->crb_cmd_producer = qlcnic_get_ioaddr(adapter,
QLCNIC_REG(temp - 0x200));
adapter->tx_context_id =
le16_to_cpu(prsp->context_id);
} else {
dev_err(&adapter->pdev->dev,
"Failed to create tx ctx in firmware%d\n", err);
err = -EIO;
}
pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
out_free_rq:
pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
return err;
}
static void
qlcnic_fw_cmd_destroy_tx_ctx(struct qlcnic_adapter *adapter)
{
if (qlcnic_issue_cmd(adapter,
adapter->ahw.pci_func,
QLCHAL_VERSION,
adapter->tx_context_id,
QLCNIC_DESTROY_CTX_RESET,
0,
QLCNIC_CDRP_CMD_DESTROY_TX_CTX)) {
dev_err(&adapter->pdev->dev,
"Failed to destroy tx ctx in firmware\n");
}
}
int
qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val)
{
if (qlcnic_issue_cmd(adapter,
adapter->ahw.pci_func,
QLCHAL_VERSION,
reg,
0,
0,
QLCNIC_CDRP_CMD_READ_PHY)) {
return -EIO;
}
return QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
}
int
qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val)
{
return qlcnic_issue_cmd(adapter,
adapter->ahw.pci_func,
QLCHAL_VERSION,
reg,
val,
0,
QLCNIC_CDRP_CMD_WRITE_PHY);
}
int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
{
void *addr;
int err;
int ring;
struct qlcnic_recv_context *recv_ctx;
struct qlcnic_host_rds_ring *rds_ring;
struct qlcnic_host_sds_ring *sds_ring;
struct qlcnic_host_tx_ring *tx_ring;
struct pci_dev *pdev = adapter->pdev;
recv_ctx = &adapter->recv_ctx;
tx_ring = adapter->tx_ring;
tx_ring->hw_consumer = (__le32 *)pci_alloc_consistent(pdev, sizeof(u32),
&tx_ring->hw_cons_phys_addr);
if (tx_ring->hw_consumer == NULL) {
dev_err(&pdev->dev, "failed to allocate tx consumer\n");
return -ENOMEM;
}
*(tx_ring->hw_consumer) = 0;
/* cmd desc ring */
addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring),
&tx_ring->phys_addr);
if (addr == NULL) {
dev_err(&pdev->dev, "failed to allocate tx desc ring\n");
return -ENOMEM;
}
tx_ring->desc_head = (struct cmd_desc_type0 *)addr;
for (ring = 0; ring < adapter->max_rds_rings; ring++) {
rds_ring = &recv_ctx->rds_rings[ring];
addr = pci_alloc_consistent(adapter->pdev,
RCV_DESC_RINGSIZE(rds_ring),
&rds_ring->phys_addr);
if (addr == NULL) {
dev_err(&pdev->dev,
"failed to allocate rds ring [%d]\n", ring);
err = -ENOMEM;
goto err_out_free;
}
rds_ring->desc_head = (struct rcv_desc *)addr;
}
for (ring = 0; ring < adapter->max_sds_rings; ring++) {
sds_ring = &recv_ctx->sds_rings[ring];
addr = pci_alloc_consistent(adapter->pdev,
STATUS_DESC_RINGSIZE(sds_ring),
&sds_ring->phys_addr);
if (addr == NULL) {
dev_err(&pdev->dev,
"failed to allocate sds ring [%d]\n", ring);
err = -ENOMEM;
goto err_out_free;
}
sds_ring->desc_head = (struct status_desc *)addr;
}
err = qlcnic_fw_cmd_create_rx_ctx(adapter);
if (err)
goto err_out_free;
err = qlcnic_fw_cmd_create_tx_ctx(adapter);
if (err)
goto err_out_free;
set_bit(__QLCNIC_FW_ATTACHED, &adapter->state);
return 0;
err_out_free:
qlcnic_free_hw_resources(adapter);
return err;
}
void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
{
struct qlcnic_recv_context *recv_ctx;
struct qlcnic_host_rds_ring *rds_ring;
struct qlcnic_host_sds_ring *sds_ring;
struct qlcnic_host_tx_ring *tx_ring;
int ring;
if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
qlcnic_fw_cmd_destroy_rx_ctx(adapter);
qlcnic_fw_cmd_destroy_tx_ctx(adapter);
/* Allow dma queues to drain after context reset */
msleep(20);
}
recv_ctx = &adapter->recv_ctx;
tx_ring = adapter->tx_ring;
if (tx_ring->hw_consumer != NULL) {
pci_free_consistent(adapter->pdev,
sizeof(u32),
tx_ring->hw_consumer,
tx_ring->hw_cons_phys_addr);
tx_ring->hw_consumer = NULL;
}
if (tx_ring->desc_head != NULL) {
pci_free_consistent(adapter->pdev,
TX_DESC_RINGSIZE(tx_ring),
tx_ring->desc_head, tx_ring->phys_addr);
tx_ring->desc_head = NULL;
}
for (ring = 0; ring < adapter->max_rds_rings; ring++) {
rds_ring = &recv_ctx->rds_rings[ring];
if (rds_ring->desc_head != NULL) {
pci_free_consistent(adapter->pdev,
RCV_DESC_RINGSIZE(rds_ring),
rds_ring->desc_head,
rds_ring->phys_addr);
rds_ring->desc_head = NULL;
}
}
for (ring = 0; ring < adapter->max_sds_rings; ring++) {
sds_ring = &recv_ctx->sds_rings[ring];
if (sds_ring->desc_head != NULL) {
pci_free_consistent(adapter->pdev,
STATUS_DESC_RINGSIZE(sds_ring),
sds_ring->desc_head,
sds_ring->phys_addr);
sds_ring->desc_head = NULL;
}
}
}

870
drivers/net/qlcnic/qlcnic_ethtool.c Normal file
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/*
* Copyright (C) 2009 - QLogic Corporation.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
* MA 02111-1307, USA.
*
* The full GNU General Public License is included in this distribution
* in the file called "COPYING".
*
*/
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/netdevice.h>
#include <linux/ethtool.h>
#include "qlcnic.h"
struct qlcnic_stats {
char stat_string[ETH_GSTRING_LEN];
int sizeof_stat;
int stat_offset;
};
#define QLC_SIZEOF(m) FIELD_SIZEOF(struct qlcnic_adapter, m)
#define QLC_OFF(m) offsetof(struct qlcnic_adapter, m)
static const struct qlcnic_stats qlcnic_gstrings_stats[] = {
{"xmit_called",
QLC_SIZEOF(stats.xmitcalled), QLC_OFF(stats.xmitcalled)},
{"xmit_finished",
QLC_SIZEOF(stats.xmitfinished), QLC_OFF(stats.xmitfinished)},
{"rx_dropped",
QLC_SIZEOF(stats.rxdropped), QLC_OFF(stats.rxdropped)},
{"tx_dropped",
QLC_SIZEOF(stats.txdropped), QLC_OFF(stats.txdropped)},
{"csummed",
QLC_SIZEOF(stats.csummed), QLC_OFF(stats.csummed)},
{"rx_pkts",
QLC_SIZEOF(stats.rx_pkts), QLC_OFF(stats.rx_pkts)},
{"lro_pkts",
QLC_SIZEOF(stats.lro_pkts), QLC_OFF(stats.lro_pkts)},
{"rx_bytes",
QLC_SIZEOF(stats.rxbytes), QLC_OFF(stats.rxbytes)},
{"tx_bytes",
QLC_SIZEOF(stats.txbytes), QLC_OFF(stats.txbytes)},
};
#define QLCNIC_STATS_LEN ARRAY_SIZE(qlcnic_gstrings_stats)
static const char qlcnic_gstrings_test[][ETH_GSTRING_LEN] = {
"Register_Test_on_offline",
"Link_Test_on_offline"
};
#define QLCNIC_TEST_LEN ARRAY_SIZE(qlcnic_gstrings_test)
#define QLCNIC_RING_REGS_COUNT 20
#define QLCNIC_RING_REGS_LEN (QLCNIC_RING_REGS_COUNT * sizeof(u32))
#define QLCNIC_MAX_EEPROM_LEN 1024
static const u32 diag_registers[] = {
CRB_CMDPEG_STATE,
CRB_RCVPEG_STATE,
CRB_XG_STATE_P3,
CRB_FW_CAPABILITIES_1,
ISR_INT_STATE_REG,
QLCNIC_CRB_DEV_REF_COUNT,
QLCNIC_CRB_DEV_STATE,
QLCNIC_CRB_DRV_STATE,
QLCNIC_CRB_DRV_SCRATCH,
QLCNIC_CRB_DEV_PARTITION_INFO,
QLCNIC_CRB_DRV_IDC_VER,
QLCNIC_PEG_ALIVE_COUNTER,
QLCNIC_PEG_HALT_STATUS1,
QLCNIC_PEG_HALT_STATUS2,
QLCNIC_CRB_PEG_NET_0+0x3c,
QLCNIC_CRB_PEG_NET_1+0x3c,
QLCNIC_CRB_PEG_NET_2+0x3c,
QLCNIC_CRB_PEG_NET_4+0x3c,
-1
};
static int qlcnic_get_regs_len(struct net_device *dev)
{
return sizeof(diag_registers) + QLCNIC_RING_REGS_LEN;
}
static int qlcnic_get_eeprom_len(struct net_device *dev)
{
return QLCNIC_FLASH_TOTAL_SIZE;
}
static void
qlcnic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
u32 fw_major, fw_minor, fw_build;
fw_major = QLCRD32(adapter, QLCNIC_FW_VERSION_MAJOR);
fw_minor = QLCRD32(adapter, QLCNIC_FW_VERSION_MINOR);
fw_build = QLCRD32(adapter, QLCNIC_FW_VERSION_SUB);
sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
strlcpy(drvinfo->driver, qlcnic_driver_name, 32);
strlcpy(drvinfo->version, QLCNIC_LINUX_VERSIONID, 32);
}
static int
qlcnic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
int check_sfp_module = 0;
u16 pcifn = adapter->ahw.pci_func;
/* read which mode */
if (adapter->ahw.port_type == QLCNIC_GBE) {
ecmd->supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full);
ecmd->advertising = (ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full |
ADVERTISED_1000baseT_Half |
ADVERTISED_1000baseT_Full);
ecmd->speed = adapter->link_speed;
ecmd->duplex = adapter->link_duplex;
ecmd->autoneg = adapter->link_autoneg;
} else if (adapter->ahw.port_type == QLCNIC_XGBE) {
u32 val;
val = QLCRD32(adapter, QLCNIC_PORT_MODE_ADDR);
if (val == QLCNIC_PORT_MODE_802_3_AP) {
ecmd->supported = SUPPORTED_1000baseT_Full;
ecmd->advertising = ADVERTISED_1000baseT_Full;
} else {
ecmd->supported = SUPPORTED_10000baseT_Full;
ecmd->advertising = ADVERTISED_10000baseT_Full;
}
if (netif_running(dev) && adapter->has_link_events) {
ecmd->speed = adapter->link_speed;
ecmd->autoneg = adapter->link_autoneg;
ecmd->duplex = adapter->link_duplex;
goto skip;
}
val = QLCRD32(adapter, P3_LINK_SPEED_REG(pcifn));
ecmd->speed = P3_LINK_SPEED_MHZ *
P3_LINK_SPEED_VAL(pcifn, val);
ecmd->duplex = DUPLEX_FULL;
ecmd->autoneg = AUTONEG_DISABLE;
} else
return -EIO;
skip:
ecmd->phy_address = adapter->physical_port;
ecmd->transceiver = XCVR_EXTERNAL;
switch (adapter->ahw.board_type) {
case QLCNIC_BRDTYPE_P3_REF_QG:
case QLCNIC_BRDTYPE_P3_4_GB:
case QLCNIC_BRDTYPE_P3_4_GB_MM:
ecmd->supported |= SUPPORTED_Autoneg;
ecmd->advertising |= ADVERTISED_Autoneg;
case QLCNIC_BRDTYPE_P3_10G_CX4:
case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
case QLCNIC_BRDTYPE_P3_10000_BASE_T:
ecmd->supported |= SUPPORTED_TP;
ecmd->advertising |= ADVERTISED_TP;
ecmd->port = PORT_TP;
ecmd->autoneg = adapter->link_autoneg;
break;
case QLCNIC_BRDTYPE_P3_IMEZ:
case QLCNIC_BRDTYPE_P3_XG_LOM:
case QLCNIC_BRDTYPE_P3_HMEZ:
ecmd->supported |= SUPPORTED_MII;
ecmd->advertising |= ADVERTISED_MII;
ecmd->port = PORT_MII;
ecmd->autoneg = AUTONEG_DISABLE;
break;
case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
ecmd->advertising |= ADVERTISED_TP;
ecmd->supported |= SUPPORTED_TP;
check_sfp_module = netif_running(dev) &&
adapter->has_link_events;
case QLCNIC_BRDTYPE_P3_10G_XFP:
ecmd->supported |= SUPPORTED_FIBRE;
ecmd->advertising |= ADVERTISED_FIBRE;
ecmd->port = PORT_FIBRE;
ecmd->autoneg = AUTONEG_DISABLE;
break;
case QLCNIC_BRDTYPE_P3_10G_TP:
if (adapter->ahw.port_type == QLCNIC_XGBE) {
ecmd->autoneg = AUTONEG_DISABLE;
ecmd->supported |= (SUPPORTED_FIBRE | SUPPORTED_TP);
ecmd->advertising |=
(ADVERTISED_FIBRE | ADVERTISED_TP);
ecmd->port = PORT_FIBRE;
check_sfp_module = netif_running(dev) &&
adapter->has_link_events;
} else {
ecmd->autoneg = AUTONEG_ENABLE;
ecmd->supported |= (SUPPORTED_TP | SUPPORTED_Autoneg);
ecmd->advertising |=
(ADVERTISED_TP | ADVERTISED_Autoneg);
ecmd->port = PORT_TP;
}
break;
default:
dev_err(&adapter->pdev->dev, "Unsupported board model %d\n",
adapter->ahw.board_type);
return -EIO;
}
if (check_sfp_module) {
switch (adapter->module_type) {
case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
case LINKEVENT_MODULE_OPTICAL_SRLR:
case LINKEVENT_MODULE_OPTICAL_LRM:
case LINKEVENT_MODULE_OPTICAL_SFP_1G:
ecmd->port = PORT_FIBRE;
break;
case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
case LINKEVENT_MODULE_TWINAX:
ecmd->port = PORT_TP;
break;
default:
ecmd->port = PORT_OTHER;
}
}
return 0;
}
static int
qlcnic_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
__u32 status;
/* read which mode */
if (adapter->ahw.port_type == QLCNIC_GBE) {
/* autonegotiation */
if (qlcnic_fw_cmd_set_phy(adapter,
QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ecmd->autoneg) != 0)
return -EIO;
else
adapter->link_autoneg = ecmd->autoneg;
if (qlcnic_fw_cmd_query_phy(adapter,
QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
&status) != 0)
return -EIO;
switch (ecmd->speed) {
case SPEED_10:
qlcnic_set_phy_speed(status, 0);
break;
case SPEED_100:
qlcnic_set_phy_speed(status, 1);
break;
case SPEED_1000:
qlcnic_set_phy_speed(status, 2);
break;
}
if (ecmd->duplex == DUPLEX_HALF)
qlcnic_clear_phy_duplex(status);
if (ecmd->duplex == DUPLEX_FULL)
qlcnic_set_phy_duplex(status);
if (qlcnic_fw_cmd_set_phy(adapter,
QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
*((int *)&status)) != 0)
return -EIO;
else {
adapter->link_speed = ecmd->speed;
adapter->link_duplex = ecmd->duplex;
}
} else
return -EOPNOTSUPP;
if (!netif_running(dev))
return 0;
dev->netdev_ops->ndo_stop(dev);
return dev->netdev_ops->ndo_open(dev);
}
static void
qlcnic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
struct qlcnic_host_sds_ring *sds_ring;
u32 *regs_buff = p;
int ring, i = 0;
memset(p, 0, qlcnic_get_regs_len(dev));
regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
(adapter->pdev)->device;
if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
return;
for (i = 0; diag_registers[i] != -1; i++)
regs_buff[i] = QLCRD32(adapter, diag_registers[i]);
regs_buff[i++] = 0xFFEFCDAB; /* Marker btw regs and ring count*/
regs_buff[i++] = 1; /* No. of tx ring */
regs_buff[i++] = le32_to_cpu(*(adapter->tx_ring->hw_consumer));
regs_buff[i++] = readl(adapter->tx_ring->crb_cmd_producer);
regs_buff[i++] = 2; /* No. of rx ring */
regs_buff[i++] = readl(recv_ctx->rds_rings[0].crb_rcv_producer);
regs_buff[i++] = readl(recv_ctx->rds_rings[1].crb_rcv_producer);
regs_buff[i++] = adapter->max_sds_rings;
for (ring = 0; ring < adapter->max_sds_rings; ring++) {
sds_ring = &(recv_ctx->sds_rings[ring]);
regs_buff[i++] = readl(sds_ring->crb_sts_consumer);
}
}
static u32 qlcnic_test_link(struct net_device *dev)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
u32 val;
val = QLCRD32(adapter, CRB_XG_STATE_P3);
val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val);
return (val == XG_LINK_UP_P3) ? 0 : 1;
}
static int
qlcnic_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
u8 *bytes)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
int offset;
int ret;
if (eeprom->len == 0)
return -EINVAL;
eeprom->magic = (adapter->pdev)->vendor |
((adapter->pdev)->device << 16);
offset = eeprom->offset;
ret = qlcnic_rom_fast_read_words(adapter, offset, bytes,
eeprom->len);
if (ret < 0)
return ret;
return 0;
}
static void
qlcnic_get_ringparam(struct net_device *dev,
struct ethtool_ringparam *ring)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
ring->rx_pending = adapter->num_rxd;
ring->rx_jumbo_pending = adapter->num_jumbo_rxd;
ring->rx_jumbo_pending += adapter->num_lro_rxd;
ring->tx_pending = adapter->num_txd;
if (adapter->ahw.port_type == QLCNIC_GBE) {
ring->rx_max_pending = MAX_RCV_DESCRIPTORS_1G;
ring->rx_jumbo_max_pending = MAX_JUMBO_RCV_DESCRIPTORS_1G;
} else {
ring->rx_max_pending = MAX_RCV_DESCRIPTORS_10G;
ring->rx_jumbo_max_pending = MAX_JUMBO_RCV_DESCRIPTORS_10G;
}
ring->tx_max_pending = MAX_CMD_DESCRIPTORS;
ring->rx_mini_max_pending = 0;
ring->rx_mini_pending = 0;
}
static u32
qlcnic_validate_ringparam(u32 val, u32 min, u32 max, char *r_name)
{
u32 num_desc;
num_desc = max(val, min);
num_desc = min(num_desc, max);
num_desc = roundup_pow_of_two(num_desc);
if (val != num_desc) {
printk(KERN_INFO "%s: setting %s ring size %d instead of %d\n",
qlcnic_driver_name, r_name, num_desc, val);
}
return num_desc;
}
static int
qlcnic_set_ringparam(struct net_device *dev,
struct ethtool_ringparam *ring)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
u16 max_rcv_desc = MAX_RCV_DESCRIPTORS_10G;
u16 max_jumbo_desc = MAX_JUMBO_RCV_DESCRIPTORS_10G;
u16 num_rxd, num_jumbo_rxd, num_txd;
if (ring->rx_mini_pending)
return -EOPNOTSUPP;
if (adapter->ahw.port_type == QLCNIC_GBE) {
max_rcv_desc = MAX_RCV_DESCRIPTORS_1G;
max_jumbo_desc = MAX_JUMBO_RCV_DESCRIPTORS_10G;
}
num_rxd = qlcnic_validate_ringparam(ring->rx_pending,
MIN_RCV_DESCRIPTORS, max_rcv_desc, "rx");
num_jumbo_rxd = qlcnic_validate_ringparam(ring->rx_jumbo_pending,
MIN_JUMBO_DESCRIPTORS, max_jumbo_desc, "rx jumbo");
num_txd = qlcnic_validate_ringparam(ring->tx_pending,
MIN_CMD_DESCRIPTORS, MAX_CMD_DESCRIPTORS, "tx");
if (num_rxd == adapter->num_rxd && num_txd == adapter->num_txd &&
num_jumbo_rxd == adapter->num_jumbo_rxd)
return 0;
adapter->num_rxd = num_rxd;
adapter->num_jumbo_rxd = num_jumbo_rxd;
adapter->num_txd = num_txd;
return qlcnic_reset_context(adapter);
}
static void
qlcnic_get_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *pause)
{
struct qlcnic_adapter *adapter = netdev_priv(netdev);
int port = adapter->physical_port;
__u32 val;
if (adapter->ahw.port_type == QLCNIC_GBE) {
if ((port < 0) || (port > QLCNIC_NIU_MAX_GBE_PORTS))
return;
/* get flow control settings */
val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port));
pause->rx_pause = qlcnic_gb_get_rx_flowctl(val);
val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL);
switch (port) {
case 0:
pause->tx_pause = !(qlcnic_gb_get_gb0_mask(val));
break;
case 1:
pause->tx_pause = !(qlcnic_gb_get_gb1_mask(val));
break;
case 2:
pause->tx_pause = !(qlcnic_gb_get_gb2_mask(val));
break;
case 3:
default:
pause->tx_pause = !(qlcnic_gb_get_gb3_mask(val));
break;
}
} else if (adapter->ahw.port_type == QLCNIC_XGBE) {
if ((port < 0) || (port > QLCNIC_NIU_MAX_XG_PORTS))
return;
pause->rx_pause = 1;
val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL);
if (port == 0)
pause->tx_pause = !(qlcnic_xg_get_xg0_mask(val));
else
pause->tx_pause = !(qlcnic_xg_get_xg1_mask(val));
} else {
dev_err(&netdev->dev, "Unknown board type: %x\n",
adapter->ahw.port_type);
}
}
static int
qlcnic_set_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *pause)
{
struct qlcnic_adapter *adapter = netdev_priv(netdev);
int port = adapter->physical_port;
__u32 val;
/* read mode */
if (adapter->ahw.port_type == QLCNIC_GBE) {
if ((port < 0) || (port > QLCNIC_NIU_MAX_GBE_PORTS))
return -EIO;
/* set flow control */
val = QLCRD32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port));
if (pause->rx_pause)
qlcnic_gb_rx_flowctl(val);
else
qlcnic_gb_unset_rx_flowctl(val);
QLCWR32(adapter, QLCNIC_NIU_GB_MAC_CONFIG_0(port),
val);
/* set autoneg */
val = QLCRD32(adapter, QLCNIC_NIU_GB_PAUSE_CTL);
switch (port) {
case 0:
if (pause->tx_pause)
qlcnic_gb_unset_gb0_mask(val);
else
qlcnic_gb_set_gb0_mask(val);
break;
case 1:
if (pause->tx_pause)
qlcnic_gb_unset_gb1_mask(val);
else
qlcnic_gb_set_gb1_mask(val);
break;
case 2:
if (pause->tx_pause)
qlcnic_gb_unset_gb2_mask(val);
else
qlcnic_gb_set_gb2_mask(val);
break;
case 3:
default:
if (pause->tx_pause)
qlcnic_gb_unset_gb3_mask(val);
else
qlcnic_gb_set_gb3_mask(val);
break;
}
QLCWR32(adapter, QLCNIC_NIU_GB_PAUSE_CTL, val);
} else if (adapter->ahw.port_type == QLCNIC_XGBE) {
if ((port < 0) || (port > QLCNIC_NIU_MAX_XG_PORTS))
return -EIO;
val = QLCRD32(adapter, QLCNIC_NIU_XG_PAUSE_CTL);
if (port == 0) {
if (pause->tx_pause)
qlcnic_xg_unset_xg0_mask(val);
else
qlcnic_xg_set_xg0_mask(val);
} else {
if (pause->tx_pause)
qlcnic_xg_unset_xg1_mask(val);
else
qlcnic_xg_set_xg1_mask(val);
}
QLCWR32(adapter, QLCNIC_NIU_XG_PAUSE_CTL, val);
} else {
dev_err(&netdev->dev, "Unknown board type: %x\n",
adapter->ahw.port_type);
}
return 0;
}
static int qlcnic_reg_test(struct net_device *dev)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
u32 data_read, data_written;
data_read = QLCRD32(adapter, QLCNIC_PCIX_PH_REG(0));
if ((data_read & 0xffff) != adapter->pdev->vendor)
return 1;
data_written = (u32)0xa5a5a5a5;
QLCWR32(adapter, CRB_SCRATCHPAD_TEST, data_written);
data_read = QLCRD32(adapter, CRB_SCRATCHPAD_TEST);
if (data_written != data_read)
return 1;
return 0;
}
static int qlcnic_get_sset_count(struct net_device *dev, int sset)
{
switch (sset) {
case ETH_SS_TEST:
return QLCNIC_TEST_LEN;
case ETH_SS_STATS:
return QLCNIC_STATS_LEN;
default:
return -EOPNOTSUPP;
}
}
static void
qlcnic_diag_test(struct net_device *dev, struct ethtool_test *eth_test,
u64 *data)
{
memset(data, 0, sizeof(u64) * QLCNIC_TEST_LEN);
data[0] = qlcnic_reg_test(dev);
if (data[0])
eth_test->flags |= ETH_TEST_FL_FAILED;
/* link test */
data[1] = (u64) qlcnic_test_link(dev);
if (data[1])
eth_test->flags |= ETH_TEST_FL_FAILED;
}
static void
qlcnic_get_strings(struct net_device *dev, u32 stringset, u8 * data)
{
int index;
switch (stringset) {
case ETH_SS_TEST:
memcpy(data, *qlcnic_gstrings_test,
QLCNIC_TEST_LEN * ETH_GSTRING_LEN);
break;
case ETH_SS_STATS:
for (index = 0; index < QLCNIC_STATS_LEN; index++) {
memcpy(data + index * ETH_GSTRING_LEN,
qlcnic_gstrings_stats[index].stat_string,
ETH_GSTRING_LEN);
}
break;
}
}
static void
qlcnic_get_ethtool_stats(struct net_device *dev,
struct ethtool_stats *stats, u64 * data)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
int index;
for (index = 0; index < QLCNIC_STATS_LEN; index++) {
char *p =
(char *)adapter +
qlcnic_gstrings_stats[index].stat_offset;
data[index] =
(qlcnic_gstrings_stats[index].sizeof_stat ==
sizeof(u64)) ? *(u64 *)p:(*(u32 *)p);
}
}
static u32 qlcnic_get_rx_csum(struct net_device *dev)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
return adapter->rx_csum;
}
static int qlcnic_set_rx_csum(struct net_device *dev, u32 data)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
adapter->rx_csum = !!data;
return 0;
}
static u32 qlcnic_get_tso(struct net_device *dev)
{
return (dev->features & (NETIF_F_TSO | NETIF_F_TSO6)) != 0;
}
static int qlcnic_set_tso(struct net_device *dev, u32 data)
{
if (data)
dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
else
dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
return 0;
}
static void
qlcnic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
u32 wol_cfg;
wol->supported = 0;
wol->wolopts = 0;
wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
if (wol_cfg & (1UL << adapter->portnum))
wol->supported |= WAKE_MAGIC;
wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
if (wol_cfg & (1UL << adapter->portnum))
wol->wolopts |= WAKE_MAGIC;
}
static int
qlcnic_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct qlcnic_adapter *adapter = netdev_priv(dev);
u32 wol_cfg;
if (wol->wolopts & ~WAKE_MAGIC)
return -EOPNOTSUPP;
wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
if (!(wol_cfg & (1 << adapter->portnum)))
return -EOPNOTSUPP;
wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
if (wol->wolopts & WAKE_MAGIC)
wol_cfg |= 1UL << adapter->portnum;
else
wol_cfg &= ~(1UL << adapter->portnum);
QLCWR32(adapter, QLCNIC_WOL_CONFIG, wol_cfg);
return 0;
}
/*
* Set the coalescing parameters. Currently only normal is supported.
* If rx_coalesce_usecs == 0 or rx_max_coalesced_frames == 0 then set the
* firmware coalescing to default.
*/
static int qlcnic_set_intr_coalesce(struct net_device *netdev,
struct ethtool_coalesce *ethcoal)
{
struct qlcnic_adapter *adapter = netdev_priv(netdev);
if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
return -EINVAL;
/*
* Return Error if unsupported values or
* unsupported parameters are set.
*/
if (ethcoal->rx_coalesce_usecs > 0xffff ||
ethcoal->rx_max_coalesced_frames > 0xffff ||
ethcoal->tx_coalesce_usecs > 0xffff ||
ethcoal->tx_max_coalesced_frames > 0xffff ||
ethcoal->rx_coalesce_usecs_irq ||
ethcoal->rx_max_coalesced_frames_irq ||
ethcoal->tx_coalesce_usecs_irq ||
ethcoal->tx_max_coalesced_frames_irq ||
ethcoal->stats_block_coalesce_usecs ||
ethcoal->use_adaptive_rx_coalesce ||
ethcoal->use_adaptive_tx_coalesce ||
ethcoal->pkt_rate_low ||
ethcoal->rx_coalesce_usecs_low ||
ethcoal->rx_max_coalesced_frames_low ||
ethcoal->tx_coalesce_usecs_low ||
ethcoal->tx_max_coalesced_frames_low ||
ethcoal->pkt_rate_high ||
ethcoal->rx_coalesce_usecs_high ||
ethcoal->rx_max_coalesced_frames_high ||
ethcoal->tx_coalesce_usecs_high ||
ethcoal->tx_max_coalesced_frames_high)
return -EINVAL;
if (!ethcoal->rx_coalesce_usecs ||
!ethcoal->rx_max_coalesced_frames) {
adapter->coal.flags = QLCNIC_INTR_DEFAULT;
adapter->coal.normal.data.rx_time_us =
QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US;
adapter->coal.normal.data.rx_packets =
QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS;
} else {
adapter->coal.flags = 0;
adapter->coal.normal.data.rx_time_us =
ethcoal->rx_coalesce_usecs;
adapter->coal.normal.data.rx_packets =
ethcoal->rx_max_coalesced_frames;
}
adapter->coal.normal.data.tx_time_us = ethcoal->tx_coalesce_usecs;
adapter->coal.normal.data.tx_packets =
ethcoal->tx_max_coalesced_frames;
qlcnic_config_intr_coalesce(adapter);
return 0;
}
static int qlcnic_get_intr_coalesce(struct net_device *netdev,
struct ethtool_coalesce *ethcoal)
{
struct qlcnic_adapter *adapter = netdev_priv(netdev);
if (adapter->is_up != QLCNIC_ADAPTER_UP_MAGIC)
return -EINVAL;
ethcoal->rx_coalesce_usecs = adapter->coal.normal.data.rx_time_us;
ethcoal->tx_coalesce_usecs = adapter->coal.normal.data.tx_time_us;
ethcoal->rx_max_coalesced_frames =
adapter->coal.normal.data.rx_packets;
ethcoal->tx_max_coalesced_frames =
adapter->coal.normal.data.tx_packets;
return 0;
}
static int qlcnic_set_flags(struct net_device *netdev, u32 data)
{
struct qlcnic_adapter *adapter = netdev_priv(netdev);
int hw_lro;
if (!(adapter->capabilities & QLCNIC_FW_CAPABILITY_HW_LRO))
return -EINVAL;
ethtool_op_set_flags(netdev, data);
hw_lro = (data & ETH_FLAG_LRO) ? QLCNIC_LRO_ENABLED : 0;
if (qlcnic_config_hw_lro(adapter, hw_lro))
return -EIO;
if ((hw_lro == 0) && qlcnic_send_lro_cleanup(adapter))
return -EIO;
return 0;
}
const struct ethtool_ops qlcnic_ethtool_ops = {
.get_settings = qlcnic_get_settings,
.set_settings = qlcnic_set_settings,
.get_drvinfo = qlcnic_get_drvinfo,
.get_regs_len = qlcnic_get_regs_len,
.get_regs = qlcnic_get_regs,
.get_link = ethtool_op_get_link,
.get_eeprom_len = qlcnic_get_eeprom_len,
.get_eeprom = qlcnic_get_eeprom,
.get_ringparam = qlcnic_get_ringparam,
.set_ringparam = qlcnic_set_ringparam,
.get_pauseparam = qlcnic_get_pauseparam,
.set_pauseparam = qlcnic_set_pauseparam,
.set_tx_csum = ethtool_op_set_tx_csum,
.set_sg = ethtool_op_set_sg,
.get_tso = qlcnic_get_tso,
.set_tso = qlcnic_set_tso,
.get_wol = qlcnic_get_wol,
.set_wol = qlcnic_set_wol,
.self_test = qlcnic_diag_test,
.get_strings = qlcnic_get_strings,
.get_ethtool_stats = qlcnic_get_ethtool_stats,
.get_sset_count = qlcnic_get_sset_count,
.get_rx_csum = qlcnic_get_rx_csum,
.set_rx_csum = qlcnic_set_rx_csum,
.get_coalesce = qlcnic_get_intr_coalesce,
.set_coalesce = qlcnic_set_intr_coalesce,
.get_flags = ethtool_op_get_flags,
.set_flags = qlcnic_set_flags,
};

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drivers/net/qlcnic/qlcnic_hdr.h Normal file
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/*
* Copyright (C) 2009 - QLogic Corporation.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
* MA 02111-1307, USA.
*
* The full GNU General Public License is included in this distribution
* in the file called "COPYING".
*
*/
#ifndef __QLCNIC_HDR_H_
#define __QLCNIC_HDR_H_
#include <linux/kernel.h>
#include <linux/types.h>
/*
* The basic unit of access when reading/writing control registers.
*/
enum {
QLCNIC_HW_H0_CH_HUB_ADR = 0x05,
QLCNIC_HW_H1_CH_HUB_ADR = 0x0E,
QLCNIC_HW_H2_CH_HUB_ADR = 0x03,
QLCNIC_HW_H3_CH_HUB_ADR = 0x01,
QLCNIC_HW_H4_CH_HUB_ADR = 0x06,
QLCNIC_HW_H5_CH_HUB_ADR = 0x07,
QLCNIC_HW_H6_CH_HUB_ADR = 0x08
};
/* Hub 0 */
enum {
QLCNIC_HW_MN_CRB_AGT_ADR = 0x15,
QLCNIC_HW_MS_CRB_AGT_ADR = 0x25
};
/* Hub 1 */
enum {
QLCNIC_HW_PS_CRB_AGT_ADR = 0x73,
QLCNIC_HW_SS_CRB_AGT_ADR = 0x20,
QLCNIC_HW_RPMX3_CRB_AGT_ADR = 0x0b,
QLCNIC_HW_QMS_CRB_AGT_ADR = 0x00,
QLCNIC_HW_SQGS0_CRB_AGT_ADR = 0x01,
QLCNIC_HW_SQGS1_CRB_AGT_ADR = 0x02,
QLCNIC_HW_SQGS2_CRB_AGT_ADR = 0x03,
QLCNIC_HW_SQGS3_CRB_AGT_ADR = 0x04,
QLCNIC_HW_C2C0_CRB_AGT_ADR = 0x58,
QLCNIC_HW_C2C1_CRB_AGT_ADR = 0x59,
QLCNIC_HW_C2C2_CRB_AGT_ADR = 0x5a,
QLCNIC_HW_RPMX2_CRB_AGT_ADR = 0x0a,
QLCNIC_HW_RPMX4_CRB_AGT_ADR = 0x0c,
QLCNIC_HW_RPMX7_CRB_AGT_ADR = 0x0f,
QLCNIC_HW_RPMX9_CRB_AGT_ADR = 0x12,
QLCNIC_HW_SMB_CRB_AGT_ADR = 0x18
};
/* Hub 2 */
enum {
QLCNIC_HW_NIU_CRB_AGT_ADR = 0x31,
QLCNIC_HW_I2C0_CRB_AGT_ADR = 0x19,
QLCNIC_HW_I2C1_CRB_AGT_ADR = 0x29,
QLCNIC_HW_SN_CRB_AGT_ADR = 0x10,
QLCNIC_HW_I2Q_CRB_AGT_ADR = 0x20,
QLCNIC_HW_LPC_CRB_AGT_ADR = 0x22,
QLCNIC_HW_ROMUSB_CRB_AGT_ADR = 0x21,
QLCNIC_HW_QM_CRB_AGT_ADR = 0x66,
QLCNIC_HW_SQG0_CRB_AGT_ADR = 0x60,
QLCNIC_HW_SQG1_CRB_AGT_ADR = 0x61,
QLCNIC_HW_SQG2_CRB_AGT_ADR = 0x62,
QLCNIC_HW_SQG3_CRB_AGT_ADR = 0x63,
QLCNIC_HW_RPMX1_CRB_AGT_ADR = 0x09,
QLCNIC_HW_RPMX5_CRB_AGT_ADR = 0x0d,
QLCNIC_HW_RPMX6_CRB_AGT_ADR = 0x0e,
QLCNIC_HW_RPMX8_CRB_AGT_ADR = 0x11
};
/* Hub 3 */
enum {
QLCNIC_HW_PH_CRB_AGT_ADR = 0x1A,
QLCNIC_HW_SRE_CRB_AGT_ADR = 0x50,
QLCNIC_HW_EG_CRB_AGT_ADR = 0x51,
QLCNIC_HW_RPMX0_CRB_AGT_ADR = 0x08
};
/* Hub 4 */
enum {
QLCNIC_HW_PEGN0_CRB_AGT_ADR = 0x40,
QLCNIC_HW_PEGN1_CRB_AGT_ADR,
QLCNIC_HW_PEGN2_CRB_AGT_ADR,
QLCNIC_HW_PEGN3_CRB_AGT_ADR,
QLCNIC_HW_PEGNI_CRB_AGT_ADR,
QLCNIC_HW_PEGND_CRB_AGT_ADR,
QLCNIC_HW_PEGNC_CRB_AGT_ADR,
QLCNIC_HW_PEGR0_CRB_AGT_ADR,
QLCNIC_HW_PEGR1_CRB_AGT_ADR,
QLCNIC_HW_PEGR2_CRB_AGT_ADR,
QLCNIC_HW_PEGR3_CRB_AGT_ADR,
QLCNIC_HW_PEGN4_CRB_AGT_ADR
};
/* Hub 5 */
enum {
QLCNIC_HW_PEGS0_CRB_AGT_ADR = 0x40,
QLCNIC_HW_PEGS1_CRB_AGT_ADR,
QLCNIC_HW_PEGS2_CRB_AGT_ADR,
QLCNIC_HW_PEGS3_CRB_AGT_ADR,
QLCNIC_HW_PEGSI_CRB_AGT_ADR,
QLCNIC_HW_PEGSD_CRB_AGT_ADR,
QLCNIC_HW_PEGSC_CRB_AGT_ADR
};
/* Hub 6 */
enum {
QLCNIC_HW_CAS0_CRB_AGT_ADR = 0x46,
QLCNIC_HW_CAS1_CRB_AGT_ADR = 0x47,
QLCNIC_HW_CAS2_CRB_AGT_ADR = 0x48,
QLCNIC_HW_CAS3_CRB_AGT_ADR = 0x49,
QLCNIC_HW_NCM_CRB_AGT_ADR = 0x16,
QLCNIC_HW_TMR_CRB_AGT_ADR = 0x17,
QLCNIC_HW_XDMA_CRB_AGT_ADR = 0x05,
QLCNIC_HW_OCM0_CRB_AGT_ADR = 0x06,
QLCNIC_HW_OCM1_CRB_AGT_ADR = 0x07
};
/* Floaters - non existent modules */
#define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR 0x67
/* This field defines PCI/X adr [25:20] of agents on the CRB */
enum {
QLCNIC_HW_PX_MAP_CRB_PH = 0,
QLCNIC_HW_PX_MAP_CRB_PS,
QLCNIC_HW_PX_MAP_CRB_MN,
QLCNIC_HW_PX_MAP_CRB_MS,
QLCNIC_HW_PX_MAP_CRB_PGR1,
QLCNIC_HW_PX_MAP_CRB_SRE,
QLCNIC_HW_PX_MAP_CRB_NIU,
QLCNIC_HW_PX_MAP_CRB_QMN,
QLCNIC_HW_PX_MAP_CRB_SQN0,
QLCNIC_HW_PX_MAP_CRB_SQN1,
QLCNIC_HW_PX_MAP_CRB_SQN2,
QLCNIC_HW_PX_MAP_CRB_SQN3,
QLCNIC_HW_PX_MAP_CRB_QMS,
QLCNIC_HW_PX_MAP_CRB_SQS0,
QLCNIC_HW_PX_MAP_CRB_SQS1,
QLCNIC_HW_PX_MAP_CRB_SQS2,
QLCNIC_HW_PX_MAP_CRB_SQS3,
QLCNIC_HW_PX_MAP_CRB_PGN0,
QLCNIC_HW_PX_MAP_CRB_PGN1,
QLCNIC_HW_PX_MAP_CRB_PGN2,
QLCNIC_HW_PX_MAP_CRB_PGN3,
QLCNIC_HW_PX_MAP_CRB_PGND,
QLCNIC_HW_PX_MAP_CRB_PGNI,
QLCNIC_HW_PX_MAP_CRB_PGS0,
QLCNIC_HW_PX_MAP_CRB_PGS1,
QLCNIC_HW_PX_MAP_CRB_PGS2,
QLCNIC_HW_PX_MAP_CRB_PGS3,
QLCNIC_HW_PX_MAP_CRB_PGSD,
QLCNIC_HW_PX_MAP_CRB_PGSI,
QLCNIC_HW_PX_MAP_CRB_SN,
QLCNIC_HW_PX_MAP_CRB_PGR2,
QLCNIC_HW_PX_MAP_CRB_EG,
QLCNIC_HW_PX_MAP_CRB_PH2,
QLCNIC_HW_PX_MAP_CRB_PS2,
QLCNIC_HW_PX_MAP_CRB_CAM,
QLCNIC_HW_PX_MAP_CRB_CAS0,
QLCNIC_HW_PX_MAP_CRB_CAS1,
QLCNIC_HW_PX_MAP_CRB_CAS2,
QLCNIC_HW_PX_MAP_CRB_C2C0,
QLCNIC_HW_PX_MAP_CRB_C2C1,
QLCNIC_HW_PX_MAP_CRB_TIMR,
QLCNIC_HW_PX_MAP_CRB_PGR3,
QLCNIC_HW_PX_MAP_CRB_RPMX1,
QLCNIC_HW_PX_MAP_CRB_RPMX2,
QLCNIC_HW_PX_MAP_CRB_RPMX3,
QLCNIC_HW_PX_MAP_CRB_RPMX4,
QLCNIC_HW_PX_MAP_CRB_RPMX5,
QLCNIC_HW_PX_MAP_CRB_RPMX6,
QLCNIC_HW_PX_MAP_CRB_RPMX7,
QLCNIC_HW_PX_MAP_CRB_XDMA,
QLCNIC_HW_PX_MAP_CRB_I2Q,
QLCNIC_HW_PX_MAP_CRB_ROMUSB,
QLCNIC_HW_PX_MAP_CRB_CAS3,
QLCNIC_HW_PX_MAP_CRB_RPMX0,
QLCNIC_HW_PX_MAP_CRB_RPMX8,
QLCNIC_HW_PX_MAP_CRB_RPMX9,
QLCNIC_HW_PX_MAP_CRB_OCM0,
QLCNIC_HW_PX_MAP_CRB_OCM1,
QLCNIC_HW_PX_MAP_CRB_SMB,
QLCNIC_HW_PX_MAP_CRB_I2C0,
QLCNIC_HW_PX_MAP_CRB_I2C1,
QLCNIC_HW_PX_MAP_CRB_LPC,
QLCNIC_HW_PX_MAP_CRB_PGNC,
QLCNIC_HW_PX_MAP_CRB_PGR0
};
/* This field defines CRB adr [31:20] of the agents */
#define QLCNIC_HW_CRB_HUB_AGT_ADR_MN \
((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PH \
((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_MS \
((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PS \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SS \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9 \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB \
((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU \
((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0 \
((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1 \
((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_EG \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3 \
((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0 \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1 \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2 \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3 \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4 \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0 \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1 \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2 \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3 \
((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI \
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD \
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0 \
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1 \
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2 \
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3 \
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC \
((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM \
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR \
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA \
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_SN \
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q \
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB \
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0 \
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1 \
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR)
#define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC \
((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR)
#define QLCNIC_SRE_MISC (QLCNIC_CRB_SRE + 0x0002c)
#define QLCNIC_I2Q_CLR_PCI_HI (QLCNIC_CRB_I2Q + 0x00034)
#define ROMUSB_GLB (QLCNIC_CRB_ROMUSB + 0x00000)
#define ROMUSB_ROM (QLCNIC_CRB_ROMUSB + 0x10000)
#define QLCNIC_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
#define QLCNIC_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
#define QLCNIC_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c)
#define QLCNIC_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
#define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044)
#define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
#define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8)
#define QLCNIC_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n)))
#define QLCNIC_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
#define QLCNIC_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
#define QLCNIC_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
#define QLCNIC_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
#define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
#define QLCNIC_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
/* Lock IDs for ROM lock */
#define ROM_LOCK_DRIVER 0x0d417340
/******************************************************************************
*
* Definitions specific to M25P flash
*
*******************************************************************************
*/
/* all are 1MB windows */
#define QLCNIC_PCI_CRB_WINDOWSIZE 0x00100000
#define QLCNIC_PCI_CRB_WINDOW(A) \
(QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE)
#define QLCNIC_CRB_NIU QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU)
#define QLCNIC_CRB_SRE QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE)
#define QLCNIC_CRB_ROMUSB \
QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB)
#define QLCNIC_CRB_I2Q QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q)
#define QLCNIC_CRB_I2C0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0)
#define QLCNIC_CRB_SMB QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB)
#define QLCNIC_CRB_MAX QLCNIC_PCI_CRB_WINDOW(64)
#define QLCNIC_CRB_PCIX_HOST QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH)
#define QLCNIC_CRB_PCIX_HOST2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2)
#define QLCNIC_CRB_PEG_NET_0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0)
#define QLCNIC_CRB_PEG_NET_1 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1)
#define QLCNIC_CRB_PEG_NET_2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2)
#define QLCNIC_CRB_PEG_NET_3 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3)
#define QLCNIC_CRB_PEG_NET_4 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2)
#define QLCNIC_CRB_PEG_NET_D QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND)
#define QLCNIC_CRB_PEG_NET_I QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI)
#define QLCNIC_CRB_DDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN)
#define QLCNIC_CRB_QDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN)
#define QLCNIC_CRB_PCIX_MD QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS)
#define QLCNIC_CRB_PCIE QLCNIC_CRB_PCIX_MD
#define ISR_INT_VECTOR (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR))
#define ISR_INT_MASK (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
#define ISR_INT_MASK_SLOW (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK))
#define ISR_INT_TARGET_STATUS (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS))
#define ISR_INT_TARGET_MASK (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK))
#define ISR_INT_TARGET_STATUS_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
#define ISR_INT_TARGET_MASK_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
#define ISR_INT_TARGET_STATUS_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
#define ISR_INT_TARGET_MASK_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
#define ISR_INT_TARGET_STATUS_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
#define ISR_INT_TARGET_MASK_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
#define ISR_INT_TARGET_STATUS_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
#define ISR_INT_TARGET_MASK_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
#define ISR_INT_TARGET_STATUS_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
#define ISR_INT_TARGET_MASK_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
#define ISR_INT_TARGET_STATUS_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
#define ISR_INT_TARGET_MASK_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
#define ISR_INT_TARGET_STATUS_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
#define ISR_INT_TARGET_MASK_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
#define QLCNIC_PCI_MN_2M (0)
#define QLCNIC_PCI_MS_2M (0x80000)
#define QLCNIC_PCI_OCM0_2M (0x000c0000UL)
#define QLCNIC_PCI_CRBSPACE (0x06000000UL)
#define QLCNIC_PCI_2MB_SIZE (0x00200000UL)
#define QLCNIC_PCI_CAMQM_2M_BASE (0x000ff800UL)
#define QLCNIC_PCI_CAMQM_2M_END (0x04800800UL)
#define QLCNIC_CRB_CAM QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM)
#define QLCNIC_ADDR_DDR_NET (0x0000000000000000ULL)
#define QLCNIC_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
#define QLCNIC_ADDR_OCM0 (0x0000000200000000ULL)
#define QLCNIC_ADDR_OCM0_MAX (0x00000002000fffffULL)
#define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL)
#define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL)
#define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL)
#define QLCNIC_ADDR_QDR_NET_MAX_P3 (0x0000000303ffffffULL)
/*
* Register offsets for MN
*/
#define QLCNIC_MIU_CONTROL (0x000)
#define QLCNIC_MIU_MN_CONTROL (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL)
/* 200ms delay in each loop */
#define QLCNIC_NIU_PHY_WAITLEN 200000
/* 10 seconds before we give up */
#define QLCNIC_NIU_PHY_WAITMAX 50
#define QLCNIC_NIU_MAX_GBE_PORTS 4
#define QLCNIC_NIU_MAX_XG_PORTS 2
#define QLCNIC_NIU_MODE (QLCNIC_CRB_NIU + 0x00000)
#define QLCNIC_NIU_GB_PAUSE_CTL (QLCNIC_CRB_NIU + 0x0030c)
#define QLCNIC_NIU_XG_PAUSE_CTL (QLCNIC_CRB_NIU + 0x00098)
#define QLCNIC_NIU_GB_MAC_CONFIG_0(I) \
(QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000)
#define QLCNIC_NIU_GB_MAC_CONFIG_1(I) \
(QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000)
#define TEST_AGT_CTRL (0x00)
#define TA_CTL_START 1
#define TA_CTL_ENABLE 2
#define TA_CTL_WRITE 4
#define TA_CTL_BUSY 8
/*
* Register offsets for MN
*/
#define MIU_TEST_AGT_BASE (0x90)
#define MIU_TEST_AGT_ADDR_LO (0x04)
#define MIU_TEST_AGT_ADDR_HI (0x08)
#define MIU_TEST_AGT_WRDATA_LO (0x10)
#define MIU_TEST_AGT_WRDATA_HI (0x14)
#define MIU_TEST_AGT_WRDATA_UPPER_LO (0x20)
#define MIU_TEST_AGT_WRDATA_UPPER_HI (0x24)
#define MIU_TEST_AGT_WRDATA(i) (0x10+(0x10*((i)>>1))+(4*((i)&1)))
#define MIU_TEST_AGT_RDDATA_LO (0x18)
#define MIU_TEST_AGT_RDDATA_HI (0x1c)
#define MIU_TEST_AGT_RDDATA_UPPER_LO (0x28)
#define MIU_TEST_AGT_RDDATA_UPPER_HI (0x2c)
#define MIU_TEST_AGT_RDDATA(i) (0x18+(0x10*((i)>>1))+(4*((i)&1)))
#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
#define MIU_TEST_AGT_UPPER_ADDR(off) (0)
/*
* Register offsets for MS
*/
#define SIU_TEST_AGT_BASE (0x60)
#define SIU_TEST_AGT_ADDR_LO (0x04)
#define SIU_TEST_AGT_ADDR_HI (0x18)
#define SIU_TEST_AGT_WRDATA_LO (0x08)
#define SIU_TEST_AGT_WRDATA_HI (0x0c)
#define SIU_TEST_AGT_WRDATA(i) (0x08+(4*(i)))
#define SIU_TEST_AGT_RDDATA_LO (0x10)
#define SIU_TEST_AGT_RDDATA_HI (0x14)
#define SIU_TEST_AGT_RDDATA(i) (0x10+(4*(i)))
#define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
#define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22)
/* XG Link status */
#define XG_LINK_UP 0x10
#define XG_LINK_DOWN 0x20
#define XG_LINK_UP_P3 0x01
#define XG_LINK_DOWN_P3 0x02
#define XG_LINK_STATE_P3_MASK 0xf
#define XG_LINK_STATE_P3(pcifn, val) \
(((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3_MASK)
#define P3_LINK_SPEED_MHZ 100
#define P3_LINK_SPEED_MASK 0xff
#define P3_LINK_SPEED_REG(pcifn) \
(CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4))
#define P3_LINK_SPEED_VAL(pcifn, reg) \
(((reg) >> (8 * ((pcifn) & 0x3))) & P3_LINK_SPEED_MASK)
#define QLCNIC_CAM_RAM_BASE (QLCNIC_CRB_CAM + 0x02000)
#define QLCNIC_CAM_RAM(reg) (QLCNIC_CAM_RAM_BASE + (reg))
#define QLCNIC_FW_VERSION_MAJOR (QLCNIC_CAM_RAM(0x150))
#define QLCNIC_FW_VERSION_MINOR (QLCNIC_CAM_RAM(0x154))
#define QLCNIC_FW_VERSION_SUB (QLCNIC_CAM_RAM(0x158))
#define QLCNIC_ROM_LOCK_ID (QLCNIC_CAM_RAM(0x100))
#define QLCNIC_PHY_LOCK_ID (QLCNIC_CAM_RAM(0x120))
#define QLCNIC_CRB_WIN_LOCK_ID (QLCNIC_CAM_RAM(0x124))
#define NIC_CRB_BASE (QLCNIC_CAM_RAM(0x200))
#define NIC_CRB_BASE_2 (QLCNIC_CAM_RAM(0x700))
#define QLCNIC_REG(X) (NIC_CRB_BASE+(X))
#define QLCNIC_REG_2(X) (NIC_CRB_BASE_2+(X))
#define QLCNIC_CDRP_CRB_OFFSET (QLCNIC_REG(0x18))
#define QLCNIC_ARG1_CRB_OFFSET (QLCNIC_REG(0x1c))
#define QLCNIC_ARG2_CRB_OFFSET (QLCNIC_REG(0x20))
#define QLCNIC_ARG3_CRB_OFFSET (QLCNIC_REG(0x24))
#define QLCNIC_SIGN_CRB_OFFSET (QLCNIC_REG(0x28))
#define CRB_CMDPEG_STATE (QLCNIC_REG(0x50))
#define CRB_RCVPEG_STATE (QLCNIC_REG(0x13c))
#define CRB_XG_STATE_P3 (QLCNIC_REG(0x98))
#define CRB_PF_LINK_SPEED_1 (QLCNIC_REG(0xe8))
#define CRB_PF_LINK_SPEED_2 (QLCNIC_REG(0xec))
#define CRB_MPORT_MODE (QLCNIC_REG(0xc4))
#define CRB_DMA_SHIFT (QLCNIC_REG(0xcc))
#define CRB_TEMP_STATE (QLCNIC_REG(0x1b4))
#define CRB_V2P_0 (QLCNIC_REG(0x290))
#define CRB_V2P(port) (CRB_V2P_0+((port)*4))
#define CRB_DRIVER_VERSION (QLCNIC_REG(0x2a0))
#define CRB_SW_INT_MASK_0 (QLCNIC_REG(0x1d8))
#define CRB_SW_INT_MASK_1 (QLCNIC_REG(0x1e0))
#define CRB_SW_INT_MASK_2 (QLCNIC_REG(0x1e4))
#define CRB_SW_INT_MASK_3 (QLCNIC_REG(0x1e8))
#define CRB_FW_CAPABILITIES_1 (QLCNIC_CAM_RAM(0x128))
#define CRB_MAC_BLOCK_START (QLCNIC_CAM_RAM(0x1c0))
/*
* capabilities register, can be used to selectively enable/disable features
* for backward compability
*/
#define CRB_NIC_CAPABILITIES_HOST QLCNIC_REG(0x1a8)
#define CRB_NIC_CAPABILITIES_FW QLCNIC_REG(0x1dc)
#define CRB_NIC_MSI_MODE_HOST QLCNIC_REG(0x270)
#define CRB_NIC_MSI_MODE_FW QLCNIC_REG(0x274)
#define INTR_SCHEME_PERPORT 0x1
#define MSI_MODE_MULTIFUNC 0x1
/* used for ethtool tests */
#define CRB_SCRATCHPAD_TEST QLCNIC_REG(0x280)
/*
* CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
* which can be read by the Phantom host to get producer/consumer indexes from
* Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
* registers will be used for the addresses of the ring's shared memory
* on the Phantom.
*/
#define qlcnic_get_temp_val(x) ((x) >> 16)
#define qlcnic_get_temp_state(x) ((x) & 0xffff)
#define qlcnic_encode_temp(val, state) (((val) << 16) | (state))
/*
* Temperature control.
*/
enum {
QLCNIC_TEMP_NORMAL = 0x1, /* Normal operating range */
QLCNIC_TEMP_WARN, /* Sound alert, temperature getting high */
QLCNIC_TEMP_PANIC /* Fatal error, hardware has shut down. */
};
/* Lock IDs for PHY lock */
#define PHY_LOCK_DRIVER 0x44524956
/* Used for PS PCI Memory access */
#define PCIX_PS_OP_ADDR_LO (0x10000)
/* via CRB (PS side only) */
#define PCIX_PS_OP_ADDR_HI (0x10004)
#define PCIX_INT_VECTOR (0x10100)
#define PCIX_INT_MASK (0x10104)
#define PCIX_OCM_WINDOW (0x10800)
#define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x20 * (func))
#define PCIX_TARGET_STATUS (0x10118)
#define PCIX_TARGET_STATUS_F1 (0x10160)
#define PCIX_TARGET_STATUS_F2 (0x10164)
#define PCIX_TARGET_STATUS_F3 (0x10168)
#define PCIX_TARGET_STATUS_F4 (0x10360)
#define PCIX_TARGET_STATUS_F5 (0x10364)
#define PCIX_TARGET_STATUS_F6 (0x10368)
#define PCIX_TARGET_STATUS_F7 (0x1036c)
#define PCIX_TARGET_MASK (0x10128)
#define PCIX_TARGET_MASK_F1 (0x10170)
#define PCIX_TARGET_MASK_F2 (0x10174)
#define PCIX_TARGET_MASK_F3 (0x10178)
#define PCIX_TARGET_MASK_F4 (0x10370)
#define PCIX_TARGET_MASK_F5 (0x10374)
#define PCIX_TARGET_MASK_F6 (0x10378)
#define PCIX_TARGET_MASK_F7 (0x1037c)
#define PCIX_MSI_F(i) (0x13000+((i)*4))
#define QLCNIC_PCIX_PH_REG(reg) (QLCNIC_CRB_PCIE + (reg))
#define QLCNIC_PCIX_PS_REG(reg) (QLCNIC_CRB_PCIX_MD + (reg))
#define QLCNIC_PCIE_REG(reg) (QLCNIC_CRB_PCIE + (reg))
#define PCIE_SEM0_LOCK (0x1c000)
#define PCIE_SEM0_UNLOCK (0x1c004)
#define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N))
#define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N))
#define PCIE_SETUP_FUNCTION (0x12040)
#define PCIE_SETUP_FUNCTION2 (0x12048)
#define PCIE_MISCCFG_RC (0x1206c)
#define PCIE_TGT_SPLIT_CHICKEN (0x12080)
#define PCIE_CHICKEN3 (0x120c8)
#define ISR_INT_STATE_REG (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC))
#define PCIE_MAX_MASTER_SPLIT (0x14048)
#define QLCNIC_PORT_MODE_NONE 0
#define QLCNIC_PORT_MODE_XG 1
#define QLCNIC_PORT_MODE_GB 2
#define QLCNIC_PORT_MODE_802_3_AP 3
#define QLCNIC_PORT_MODE_AUTO_NEG 4
#define QLCNIC_PORT_MODE_AUTO_NEG_1G 5
#define QLCNIC_PORT_MODE_AUTO_NEG_XG 6
#define QLCNIC_PORT_MODE_ADDR (QLCNIC_CAM_RAM(0x24))
#define QLCNIC_WOL_PORT_MODE (QLCNIC_CAM_RAM(0x198))
#define QLCNIC_WOL_CONFIG_NV (QLCNIC_CAM_RAM(0x184))
#define QLCNIC_WOL_CONFIG (QLCNIC_CAM_RAM(0x188))
#define QLCNIC_PEG_TUNE_MN_PRESENT 0x1
#define QLCNIC_PEG_TUNE_CAPABILITY (QLCNIC_CAM_RAM(0x02c))
#define QLCNIC_DMA_WATCHDOG_CTRL (QLCNIC_CAM_RAM(0x14))
#define QLCNIC_PEG_ALIVE_COUNTER (QLCNIC_CAM_RAM(0xb0))
#define QLCNIC_PEG_HALT_STATUS1 (QLCNIC_CAM_RAM(0xa8))
#define QLCNIC_PEG_HALT_STATUS2 (QLCNIC_CAM_RAM(0xac))
#define QLCNIC_CRB_DEV_REF_COUNT (QLCNIC_CAM_RAM(0x138))
#define QLCNIC_CRB_DEV_STATE (QLCNIC_CAM_RAM(0x140))
#define QLCNIC_CRB_DRV_STATE (QLCNIC_CAM_RAM(0x144))
#define QLCNIC_CRB_DRV_SCRATCH (QLCNIC_CAM_RAM(0x148))
#define QLCNIC_CRB_DEV_PARTITION_INFO (QLCNIC_CAM_RAM(0x14c))
#define QLCNIC_CRB_DRV_IDC_VER (QLCNIC_CAM_RAM(0x14c))
/* Device State */
#define QLCNIC_DEV_COLD 1
#define QLCNIC_DEV_INITALIZING 2
#define QLCNIC_DEV_READY 3
#define QLCNIC_DEV_NEED_RESET 4
#define QLCNIC_DEV_NEED_QUISCENT 5
#define QLCNIC_DEV_FAILED 6
#define QLCNIC_RCODE_DRIVER_INFO 0x20000000
#define QLCNIC_RCODE_DRIVER_CAN_RELOAD 0x40000000
#define QLCNIC_RCODE_FATAL_ERROR 0x80000000
#define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff)
#define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0xfffff)
#define FW_POLL_DELAY (2 * HZ)
#define FW_FAIL_THRESH 3
#define FW_POLL_THRESH 10
#define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
#define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
/*
* PCI Interrupt Vector Values.
*/
#define PCIX_INT_VECTOR_BIT_F0 0x0080
#define PCIX_INT_VECTOR_BIT_F1 0x0100
#define PCIX_INT_VECTOR_BIT_F2 0x0200
#define PCIX_INT_VECTOR_BIT_F3 0x0400
#define PCIX_INT_VECTOR_BIT_F4 0x0800
#define PCIX_INT_VECTOR_BIT_F5 0x1000
#define PCIX_INT_VECTOR_BIT_F6 0x2000
#define PCIX_INT_VECTOR_BIT_F7 0x4000
struct qlcnic_legacy_intr_set {
u32 int_vec_bit;
u32 tgt_status_reg;
u32 tgt_mask_reg;
u32 pci_int_reg;
};
#define QLCNIC_LEGACY_INTR_CONFIG \
{ \
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
.tgt_status_reg = ISR_INT_TARGET_STATUS, \
.tgt_mask_reg = ISR_INT_TARGET_MASK, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
\
{ \
.int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
.tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
.tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
.pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
}
/* NIU REGS */
#define _qlcnic_crb_get_bit(var, bit) ((var >> bit) & 0x1)
/*
* NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
*
* Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
* Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
* Bit 2 : enable_rx => 1:enable frame recv, 0:disable
* Bit 3 : rx_synced => R/O: recv enable synched to recv stream
* Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
* Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
* Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
* Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
* Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
* Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
* Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
* Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
*/
#define qlcnic_gb_rx_flowctl(config_word) \
((config_word) |= 1 << 5)
#define qlcnic_gb_get_rx_flowctl(config_word) \
_qlcnic_crb_get_bit((config_word), 5)
#define qlcnic_gb_unset_rx_flowctl(config_word) \
((config_word) &= ~(1 << 5))
/*
* NIU GB Pause Ctl Register
*/
#define qlcnic_gb_set_gb0_mask(config_word) \
((config_word) |= 1 << 0)
#define qlcnic_gb_set_gb1_mask(config_word) \
((config_word) |= 1 << 2)
#define qlcnic_gb_set_gb2_mask(config_word) \
((config_word) |= 1 << 4)
#define qlcnic_gb_set_gb3_mask(config_word) \
((config_word) |= 1 << 6)
#define qlcnic_gb_get_gb0_mask(config_word) \
_qlcnic_crb_get_bit((config_word), 0)
#define qlcnic_gb_get_gb1_mask(config_word) \
_qlcnic_crb_get_bit((config_word), 2)
#define qlcnic_gb_get_gb2_mask(config_word) \
_qlcnic_crb_get_bit((config_word), 4)
#define qlcnic_gb_get_gb3_mask(config_word) \
_qlcnic_crb_get_bit((config_word), 6)
#define qlcnic_gb_unset_gb0_mask(config_word) \
((config_word) &= ~(1 << 0))
#define qlcnic_gb_unset_gb1_mask(config_word) \
((config_word) &= ~(1 << 2))
#define qlcnic_gb_unset_gb2_mask(config_word) \
((config_word) &= ~(1 << 4))
#define qlcnic_gb_unset_gb3_mask(config_word) \
((config_word) &= ~(1 << 6))
/*
* NIU XG Pause Ctl Register
*
* Bit 0 : xg0_mask => 1:disable tx pause frames
* Bit 1 : xg0_request => 1:request single pause frame
* Bit 2 : xg0_on_off => 1:request is pause on, 0:off
* Bit 3 : xg1_mask => 1:disable tx pause frames
* Bit 4 : xg1_request => 1:request single pause frame
* Bit 5 : xg1_on_off => 1:request is pause on, 0:off
*/
#define qlcnic_xg_set_xg0_mask(config_word) \
((config_word) |= 1 << 0)
#define qlcnic_xg_set_xg1_mask(config_word) \
((config_word) |= 1 << 3)
#define qlcnic_xg_get_xg0_mask(config_word) \
_qlcnic_crb_get_bit((config_word), 0)
#define qlcnic_xg_get_xg1_mask(config_word) \
_qlcnic_crb_get_bit((config_word), 3)
#define qlcnic_xg_unset_xg0_mask(config_word) \
((config_word) &= ~(1 << 0))
#define qlcnic_xg_unset_xg1_mask(config_word) \
((config_word) &= ~(1 << 3))
/*
* NIU XG Pause Ctl Register
*
* Bit 0 : xg0_mask => 1:disable tx pause frames
* Bit 1 : xg0_request => 1:request single pause frame
* Bit 2 : xg0_on_off => 1:request is pause on, 0:off
* Bit 3 : xg1_mask => 1:disable tx pause frames
* Bit 4 : xg1_request => 1:request single pause frame
* Bit 5 : xg1_on_off => 1:request is pause on, 0:off
*/
/*
* PHY-Specific MII control/status registers.
*/
#define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG 4
#define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17
/*
* PHY-Specific Status Register (reg 17).
*
* Bit 0 : jabber => 1:jabber detected, 0:not
* Bit 1 : polarity => 1:polarity reversed, 0:normal
* Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
* Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
* Bit 4 : energydetect => 1:sleep, 0:active
* Bit 5 : downshift => 1:downshift, 0:no downshift
* Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
* Bits 7-9 : cablelen => not valid in 10Mb/s mode
* 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
* Bit 10 : link => 1:link up, 0:link down
* Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
* Bit 12 : pagercvd => 1:page received, 0:page not received
* Bit 13 : duplex => 1:full duplex, 0:half duplex
* Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
*/
#define qlcnic_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
#define qlcnic_set_phy_speed(config_word, val) \
((config_word) |= ((val & 0x03) << 14))
#define qlcnic_set_phy_duplex(config_word) \
((config_word) |= 1 << 13)
#define qlcnic_clear_phy_duplex(config_word) \
((config_word) &= ~(1 << 13))
#define qlcnic_get_phy_link(config_word) \
_qlcnic_crb_get_bit(config_word, 10)
#define qlcnic_get_phy_duplex(config_word) \
_qlcnic_crb_get_bit(config_word, 13)
#define QLCNIC_NIU_NON_PROMISC_MODE 0
#define QLCNIC_NIU_PROMISC_MODE 1
#define QLCNIC_NIU_ALLMULTI_MODE 2
struct crb_128M_2M_sub_block_map {
unsigned valid;
unsigned start_128M;
unsigned end_128M;
unsigned start_2M;
};
struct crb_128M_2M_block_map{
struct crb_128M_2M_sub_block_map sub_block[16];
};
#endif /* __QLCNIC_HDR_H_ */

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drivers/net/qlcnic/qlcnic_hw.c Normal file
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drivers/net/qlcnic/qlcnic_init.c Normal file
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drivers/net/qlcnic/qlcnic_main.c Normal file
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