Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into drm-next
Highlights: - Cooling device support from Russell, to allow GPU throttling on system thermal overload. - Explicit fencing support from Philipp, implemented in a similar way to drm/msm. * 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux: drm/etnaviv: submit support for out-fences drm/etnaviv: return GPU fence through the submit structure drm/etnaviv: submit support for in-fences drm/etnaviv: add etnaviv cooling device drm/etnaviv: switch to postclose drm/etnaviv: add lockdep assert to fence allocation
This commit is contained in:
Dave Airlie
commit
aed93ee7d0
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@ -5,6 +5,7 @@ config DRM_ETNAVIV
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depends on ARCH_MXC || ARCH_DOVE || (ARM && COMPILE_TEST)
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depends on MMU
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select SHMEM
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select SYNC_FILE
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select TMPFS
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select IOMMU_API
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select IOMMU_SUPPORT
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@ -111,7 +111,7 @@ static int etnaviv_open(struct drm_device *dev, struct drm_file *file)
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return 0;
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}
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static void etnaviv_preclose(struct drm_device *dev, struct drm_file *file)
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static void etnaviv_postclose(struct drm_device *dev, struct drm_file *file)
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{
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struct etnaviv_drm_private *priv = dev->dev_private;
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struct etnaviv_file_private *ctx = file->driver_priv;
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@ -488,7 +488,7 @@ static struct drm_driver etnaviv_drm_driver = {
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DRIVER_PRIME |
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DRIVER_RENDER,
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.open = etnaviv_open,
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.preclose = etnaviv_preclose,
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.postclose = etnaviv_postclose,
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.gem_free_object_unlocked = etnaviv_gem_free_object,
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.gem_vm_ops = &vm_ops,
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.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
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@ -512,7 +512,7 @@ static struct drm_driver etnaviv_drm_driver = {
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.desc = "etnaviv DRM",
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.date = "20151214",
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.major = 1,
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.minor = 0,
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.minor = 1,
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};
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/*
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@ -20,6 +20,7 @@
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#include <linux/reservation.h>
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#include "etnaviv_drv.h"
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struct dma_fence;
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struct etnaviv_gem_ops;
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struct etnaviv_gem_object;
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@ -104,9 +105,10 @@ struct etnaviv_gem_submit {
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struct drm_device *dev;
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struct etnaviv_gpu *gpu;
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struct ww_acquire_ctx ticket;
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u32 fence;
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struct dma_fence *fence;
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unsigned int nr_bos;
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struct etnaviv_gem_submit_bo bos[0];
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u32 flags;
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};
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int etnaviv_gem_wait_bo(struct etnaviv_gpu *gpu, struct drm_gem_object *obj,
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@ -14,7 +14,9 @@
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/dma-fence-array.h>
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#include <linux/reservation.h>
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#include <linux/sync_file.h>
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#include "etnaviv_cmdbuf.h"
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#include "etnaviv_drv.h"
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#include "etnaviv_gpu.h"
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@ -169,8 +171,10 @@ static int submit_fence_sync(const struct etnaviv_gem_submit *submit)
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for (i = 0; i < submit->nr_bos; i++) {
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struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
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bool write = submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE;
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bool explicit = !(submit->flags & ETNA_SUBMIT_NO_IMPLICIT);
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ret = etnaviv_gpu_fence_sync_obj(etnaviv_obj, context, write);
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ret = etnaviv_gpu_fence_sync_obj(etnaviv_obj, context, write,
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explicit);
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if (ret)
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break;
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}
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@ -290,6 +294,7 @@ static void submit_cleanup(struct etnaviv_gem_submit *submit)
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}
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ww_acquire_fini(&submit->ticket);
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dma_fence_put(submit->fence);
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kfree(submit);
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}
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@ -303,6 +308,9 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
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struct etnaviv_gem_submit *submit;
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struct etnaviv_cmdbuf *cmdbuf;
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struct etnaviv_gpu *gpu;
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struct dma_fence *in_fence = NULL;
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struct sync_file *sync_file = NULL;
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int out_fence_fd = -1;
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void *stream;
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int ret;
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@ -326,6 +334,11 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
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return -EINVAL;
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}
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if (args->flags & ~ETNA_SUBMIT_FLAGS) {
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DRM_ERROR("invalid flags: 0x%x\n", args->flags);
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return -EINVAL;
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}
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/*
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* Copy the command submission and bo array to kernel space in
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* one go, and do this outside of any locks.
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@ -365,12 +378,22 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
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goto err_submit_cmds;
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}
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if (args->flags & ETNA_SUBMIT_FENCE_FD_OUT) {
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out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
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if (out_fence_fd < 0) {
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ret = out_fence_fd;
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goto err_submit_cmds;
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}
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}
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submit = submit_create(dev, gpu, args->nr_bos);
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if (!submit) {
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ret = -ENOMEM;
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goto err_submit_cmds;
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}
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submit->flags = args->flags;
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ret = submit_lookup_objects(submit, file, bos, args->nr_bos);
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if (ret)
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goto err_submit_objects;
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@ -385,6 +408,24 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
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goto err_submit_objects;
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}
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if (args->flags & ETNA_SUBMIT_FENCE_FD_IN) {
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in_fence = sync_file_get_fence(args->fence_fd);
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if (!in_fence) {
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ret = -EINVAL;
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goto err_submit_objects;
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}
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/*
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* Wait if the fence is from a foreign context, or if the fence
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* array contains any fence from a foreign context.
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*/
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if (!dma_fence_match_context(in_fence, gpu->fence_context)) {
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ret = dma_fence_wait(in_fence, true);
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if (ret)
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goto err_submit_objects;
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}
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}
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ret = submit_fence_sync(submit);
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if (ret)
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goto err_submit_objects;
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@ -405,7 +446,23 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
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if (ret == 0)
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cmdbuf = NULL;
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args->fence = submit->fence;
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if (args->flags & ETNA_SUBMIT_FENCE_FD_OUT) {
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/*
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* This can be improved: ideally we want to allocate the sync
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* file before kicking off the GPU job and just attach the
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* fence to the sync file here, eliminating the ENOMEM
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* possibility at this stage.
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*/
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sync_file = sync_file_create(submit->fence);
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if (!sync_file) {
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ret = -ENOMEM;
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goto out;
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}
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fd_install(out_fence_fd, sync_file->file);
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}
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args->fence_fd = out_fence_fd;
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args->fence = submit->fence->seqno;
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out:
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submit_unpin_objects(submit);
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@ -419,9 +476,13 @@ out:
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flush_workqueue(priv->wq);
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err_submit_objects:
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if (in_fence)
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dma_fence_put(in_fence);
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submit_cleanup(submit);
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err_submit_cmds:
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if (ret && (out_fence_fd >= 0))
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put_unused_fd(out_fence_fd);
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/* if we still own the cmdbuf */
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if (cmdbuf)
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etnaviv_cmdbuf_free(cmdbuf);
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@ -18,6 +18,7 @@
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#include <linux/dma-fence.h>
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#include <linux/moduleparam.h>
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#include <linux/of_device.h>
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#include <linux/thermal.h>
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#include "etnaviv_cmdbuf.h"
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#include "etnaviv_dump.h"
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@ -409,6 +410,17 @@ static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
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gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
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}
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static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
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{
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unsigned int fscale = 1 << (6 - gpu->freq_scale);
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u32 clock;
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clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
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VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
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etnaviv_gpu_load_clock(gpu, clock);
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}
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static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
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{
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u32 control, idle;
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@ -426,11 +438,10 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
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timeout = jiffies + msecs_to_jiffies(1000);
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while (time_is_after_jiffies(timeout)) {
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control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
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VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
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/* enable clock */
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etnaviv_gpu_load_clock(gpu, control);
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etnaviv_gpu_update_clock(gpu);
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control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
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/* Wait for stable clock. Vivante's code waited for 1ms */
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usleep_range(1000, 10000);
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@ -490,11 +501,7 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
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}
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/* We rely on the GPU running, so program the clock */
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control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
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VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
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/* enable clock */
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etnaviv_gpu_load_clock(gpu, control);
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etnaviv_gpu_update_clock(gpu);
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return 0;
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}
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@ -1051,6 +1058,12 @@ static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_fence *f;
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/*
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* GPU lock must already be held, otherwise fence completion order might
|
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* not match the seqno order assigned here.
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*/
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lockdep_assert_held(&gpu->lock);
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|
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f = kzalloc(sizeof(*f), GFP_KERNEL);
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if (!f)
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return NULL;
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@ -1064,7 +1077,7 @@ static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
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}
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int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
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unsigned int context, bool exclusive)
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unsigned int context, bool exclusive, bool explicit)
|
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{
|
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struct reservation_object *robj = etnaviv_obj->resv;
|
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struct reservation_object_list *fobj;
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|
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@ -1077,6 +1090,9 @@ int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
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return ret;
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}
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|
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if (explicit)
|
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return 0;
|
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|
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/*
|
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* If we have any shared fences, then the exclusive fence
|
||||
* should be ignored as it will already have been signalled.
|
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|
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@ -1321,8 +1337,8 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
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mutex_lock(&gpu->lock);
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gpu->event[event].fence = fence;
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submit->fence = fence->seqno;
|
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gpu->active_fence = submit->fence;
|
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submit->fence = dma_fence_get(fence);
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gpu->active_fence = submit->fence->seqno;
|
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|
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if (gpu->lastctx != cmdbuf->ctx) {
|
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gpu->mmu->need_flush = true;
|
||||
|
|
@ -1526,17 +1542,13 @@ static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
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|||
#ifdef CONFIG_PM
|
||||
static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
|
||||
{
|
||||
u32 clock;
|
||||
int ret;
|
||||
|
||||
ret = mutex_lock_killable(&gpu->lock);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
|
||||
VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
|
||||
|
||||
etnaviv_gpu_load_clock(gpu, clock);
|
||||
etnaviv_gpu_update_clock(gpu);
|
||||
etnaviv_gpu_hw_init(gpu);
|
||||
|
||||
gpu->switch_context = true;
|
||||
|
|
@ -1548,6 +1560,47 @@ static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
|
|||
}
|
||||
#endif
|
||||
|
||||
static int
|
||||
etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
|
||||
unsigned long *state)
|
||||
{
|
||||
*state = 6;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
|
||||
unsigned long *state)
|
||||
{
|
||||
struct etnaviv_gpu *gpu = cdev->devdata;
|
||||
|
||||
*state = gpu->freq_scale;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
|
||||
unsigned long state)
|
||||
{
|
||||
struct etnaviv_gpu *gpu = cdev->devdata;
|
||||
|
||||
mutex_lock(&gpu->lock);
|
||||
gpu->freq_scale = state;
|
||||
if (!pm_runtime_suspended(gpu->dev))
|
||||
etnaviv_gpu_update_clock(gpu);
|
||||
mutex_unlock(&gpu->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct thermal_cooling_device_ops cooling_ops = {
|
||||
.get_max_state = etnaviv_gpu_cooling_get_max_state,
|
||||
.get_cur_state = etnaviv_gpu_cooling_get_cur_state,
|
||||
.set_cur_state = etnaviv_gpu_cooling_set_cur_state,
|
||||
};
|
||||
|
||||
static int etnaviv_gpu_bind(struct device *dev, struct device *master,
|
||||
void *data)
|
||||
{
|
||||
|
|
@ -1556,13 +1609,20 @@ static int etnaviv_gpu_bind(struct device *dev, struct device *master,
|
|||
struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
|
||||
(char *)dev_name(dev), gpu, &cooling_ops);
|
||||
if (IS_ERR(gpu->cooling))
|
||||
return PTR_ERR(gpu->cooling);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
ret = pm_runtime_get_sync(gpu->dev);
|
||||
#else
|
||||
ret = etnaviv_gpu_clk_enable(gpu);
|
||||
#endif
|
||||
if (ret < 0)
|
||||
if (ret < 0) {
|
||||
thermal_cooling_device_unregister(gpu->cooling);
|
||||
return ret;
|
||||
}
|
||||
|
||||
gpu->drm = drm;
|
||||
gpu->fence_context = dma_fence_context_alloc(1);
|
||||
|
|
@ -1616,6 +1676,9 @@ static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
|
|||
}
|
||||
|
||||
gpu->drm = NULL;
|
||||
|
||||
thermal_cooling_device_unregister(gpu->cooling);
|
||||
gpu->cooling = NULL;
|
||||
}
|
||||
|
||||
static const struct component_ops gpu_ops = {
|
||||
|
|
|
|||
|
|
@ -97,6 +97,7 @@ struct etnaviv_cmdbuf;
|
|||
|
||||
struct etnaviv_gpu {
|
||||
struct drm_device *drm;
|
||||
struct thermal_cooling_device *cooling;
|
||||
struct device *dev;
|
||||
struct mutex lock;
|
||||
struct etnaviv_chip_identity identity;
|
||||
|
|
@ -150,6 +151,7 @@ struct etnaviv_gpu {
|
|||
u32 hangcheck_fence;
|
||||
u32 hangcheck_dma_addr;
|
||||
struct work_struct recover_work;
|
||||
unsigned int freq_scale;
|
||||
};
|
||||
|
||||
static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
|
||||
|
|
@ -181,7 +183,7 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
|
|||
#endif
|
||||
|
||||
int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
|
||||
unsigned int context, bool exclusive);
|
||||
unsigned int context, bool exclusive, bool implicit);
|
||||
|
||||
void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
|
||||
int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
|
||||
|
|
|
|||
|
|
@ -154,6 +154,12 @@ struct drm_etnaviv_gem_submit_bo {
|
|||
* one or more cmdstream buffers. This allows for conditional execution
|
||||
* (context-restore), and IB buffers needed for per tile/bin draw cmds.
|
||||
*/
|
||||
#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
|
||||
#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
|
||||
#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
|
||||
#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
|
||||
ETNA_SUBMIT_FENCE_FD_IN | \
|
||||
ETNA_SUBMIT_FENCE_FD_OUT)
|
||||
#define ETNA_PIPE_3D 0x00
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#define ETNA_PIPE_2D 0x01
|
||||
#define ETNA_PIPE_VG 0x02
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@ -167,6 +173,8 @@ struct drm_etnaviv_gem_submit {
|
|||
__u64 bos; /* in, ptr to array of submit_bo's */
|
||||
__u64 relocs; /* in, ptr to array of submit_reloc's */
|
||||
__u64 stream; /* in, ptr to cmdstream */
|
||||
__u32 flags; /* in, mask of ETNA_SUBMIT_x */
|
||||
__s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
|
||||
};
|
||||
|
||||
/* The normal way to synchronize with the GPU is just to CPU_PREP on
|
||||
|
|
|
|||
Loading…
Reference in New Issue