usb: renesas_usbhs: Add support for RZ/A1
This patch adds the capability to support RZ/A1 SoCs. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -5,7 +5,7 @@
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obj-$(CONFIG_USB_RENESAS_USBHS) += renesas_usbhs.o
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renesas_usbhs-y := common.o mod.o pipe.o fifo.o rcar2.o rcar3.o
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renesas_usbhs-y := common.o mod.o pipe.o fifo.o rcar2.o rcar3.o rza.o
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ifneq ($(CONFIG_USB_RENESAS_USBHS_HCD),)
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renesas_usbhs-y += mod_host.o
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@ -17,6 +17,7 @@
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#include "common.h"
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#include "rcar2.h"
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#include "rcar3.h"
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#include "rza.h"
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/*
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* image of renesas_usbhs
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@ -488,6 +489,10 @@ static const struct of_device_id usbhs_of_match[] = {
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.compatible = "renesas,rcar-gen3-usbhs",
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.data = (void *)USBHS_TYPE_RCAR_GEN3,
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},
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{
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.compatible = "renesas,rza1-usbhs",
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.data = (void *)USBHS_TYPE_RZA1,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, usbhs_of_match);
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@ -520,6 +525,11 @@ static struct renesas_usbhs_platform_info *usbhs_parse_dt(struct device *dev)
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dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
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}
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if (dparam->type == USBHS_TYPE_RZA1) {
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dparam->pipe_configs = usbhsc_new_pipe;
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dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
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}
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return info;
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}
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@ -591,6 +601,9 @@ static int usbhs_probe(struct platform_device *pdev)
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dev_err(&pdev->dev, "no notifier registered\n");
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}
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break;
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case USBHS_TYPE_RZA1:
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priv->pfunc = usbhs_rza1_ops;
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break;
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default:
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if (!info->platform_callback.get_id) {
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dev_err(&pdev->dev, "no platform callbacks");
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@ -98,6 +98,7 @@ struct usbhs_priv;
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#define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
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#define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
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#define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
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#define SUSPMODE 0x0102 /* for RZ/A */
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/* SYSCFG */
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#define SCKE (1 << 10) /* USB Module Clock Enable */
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@ -106,6 +107,8 @@ struct usbhs_priv;
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#define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
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#define DPRPU (1 << 4) /* D+ Line Resistance Control */
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#define USBE (1 << 0) /* USB Module Operation Enable */
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#define UCKSEL (1 << 2) /* Clock Select for RZ/A1 */
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#define UPLLE (1 << 1) /* USB PLL Enable for RZ/A1 */
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/* DVSTCTR */
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#define EXTLP (1 << 10) /* Controls the EXTLP pin output state */
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@ -233,6 +236,9 @@ struct usbhs_priv;
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#define USBSPD_SPEED_FULL 0x2
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#define USBSPD_SPEED_HIGH 0x3
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/* SUSPMODE */
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#define SUSPM (1 << 14) /* SuspendM Control */
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/*
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* struct
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*/
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@ -0,0 +1,52 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas USB driver RZ/A initialization and power control
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*
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* Copyright (C) 2018 Chris Brandt
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* Copyright (C) 2018 Renesas Electronics Corporation
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include "common.h"
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#include "rza.h"
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static int usbhs_rza1_hardware_init(struct platform_device *pdev)
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{
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struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
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struct device_node *usb_x1_clk, *extal_clk;
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u32 freq_usb = 0, freq_extal = 0;
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/* Input Clock Selection (NOTE: ch0 controls both ch0 and ch1) */
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usb_x1_clk = of_find_node_by_name(NULL, "usb_x1");
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extal_clk = of_find_node_by_name(NULL, "extal");
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of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb);
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of_property_read_u32(extal_clk, "clock-frequency", &freq_extal);
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if (freq_usb == 0) {
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if (freq_extal == 12000000) {
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/* Select 12MHz XTAL */
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usbhs_bset(priv, SYSCFG, UCKSEL, UCKSEL);
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} else {
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dev_err(usbhs_priv_to_dev(priv), "A 48MHz USB clock or 12MHz main clock is required.\n");
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return -EIO;
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}
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}
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/* Enable USB PLL (NOTE: ch0 controls both ch0 and ch1) */
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usbhs_bset(priv, SYSCFG, UPLLE, UPLLE);
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udelay(1000);
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usbhs_bset(priv, SUSPMODE, SUSPM, SUSPM);
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return 0;
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}
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static int usbhs_rza_get_id(struct platform_device *pdev)
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{
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return USBHS_GADGET;
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}
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const struct renesas_usbhs_platform_callback usbhs_rza1_ops = {
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.hardware_init = usbhs_rza1_hardware_init,
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.get_id = usbhs_rza_get_id,
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};
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@ -0,0 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0
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#include "common.h"
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extern const struct renesas_usbhs_platform_callback usbhs_rza1_ops;
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@ -195,6 +195,7 @@ struct renesas_usbhs_driver_param {
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#define USBHS_TYPE_RCAR_GEN2 1
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#define USBHS_TYPE_RCAR_GEN3 2
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#define USBHS_TYPE_RCAR_GEN3_WITH_PLL 3
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#define USBHS_TYPE_RZA1 4
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/*
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* option:
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