Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc fixes from Benjamin Herrenschmidt: "This is purely regressions (though not all recent ones) or stable material" * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc: Partial revert of "Context switch more PMU related SPRs" powerpc/perf: Fix deadlock caused by calling printk() in PMU exception powerpc/hw_breakpoints: Add DABRX cpu feature to fix 32-bit regression powerpc/power8: Update denormalization handler powerpc/pseries: Simplify denormalization handler powerpc/power8: Fix oprofile and perf powerpc/eeh: Don't check RTAS token to get PE addr powerpc/pci: Check the bus address instead of resource address in pcibios_fixup_resources
This commit is contained in:
commit
ae75d84f3e
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@ -176,6 +176,7 @@ extern const char *powerpc_base_platform;
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#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
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#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
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#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
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#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
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#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
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#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
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#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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@ -394,19 +395,20 @@ extern const char *powerpc_base_platform;
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
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CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
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CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
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CPU_FTR_HVMODE)
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CPU_FTR_HVMODE | CPU_FTR_DABRX)
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#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
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#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_COHERENT_ICACHE | \
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CPU_FTR_COHERENT_ICACHE | \
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
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CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
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CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
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CPU_FTR_DABRX)
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#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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@ -415,7 +417,7 @@ extern const char *powerpc_base_platform;
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CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
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CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
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CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
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CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
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CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
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CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
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#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_MMCRA | CPU_FTR_SMT | \
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@ -430,14 +432,15 @@ extern const char *powerpc_base_platform;
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
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CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
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CPU_FTR_UNALIGNED_LD_STD)
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CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
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#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_PURR | CPU_FTR_REAL_LE)
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CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
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#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
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#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
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#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
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#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
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CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
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CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
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CPU_FTR_ICSWX | CPU_FTR_DABRX )
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#ifdef __powerpc64__
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#ifdef __powerpc64__
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#ifdef CONFIG_PPC_BOOK3E
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#ifdef CONFIG_PPC_BOOK3E
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@ -452,8 +452,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.mmu_features = MMU_FTRS_POWER8,
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.mmu_features = MMU_FTRS_POWER8,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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.oprofile_type = PPC_OPROFILE_POWER4,
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.oprofile_type = PPC_OPROFILE_INVALID,
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.oprofile_cpu_type = 0,
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.oprofile_cpu_type = "ppc64/ibm-compat-v1",
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.cpu_setup = __setup_cpu_power8,
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.cpu_setup = __setup_cpu_power8,
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.cpu_restore = __restore_cpu_power8,
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.cpu_restore = __restore_cpu_power8,
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.platform = "power8",
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.platform = "power8",
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@ -506,8 +506,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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.num_pmcs = 6,
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.num_pmcs = 6,
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.pmc_type = PPC_PMC_IBM,
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.pmc_type = PPC_PMC_IBM,
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.oprofile_cpu_type = 0,
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.oprofile_cpu_type = "ppc64/power8",
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.oprofile_type = PPC_OPROFILE_POWER4,
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.oprofile_type = PPC_OPROFILE_INVALID,
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.cpu_setup = __setup_cpu_power8,
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.cpu_setup = __setup_cpu_power8,
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.cpu_restore = __restore_cpu_power8,
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.cpu_restore = __restore_cpu_power8,
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.platform = "power8",
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.platform = "power8",
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@ -465,20 +465,6 @@ BEGIN_FTR_SECTION
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std r0, THREAD_EBBHR(r3)
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std r0, THREAD_EBBHR(r3)
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mfspr r0, SPRN_EBBRR
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mfspr r0, SPRN_EBBRR
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std r0, THREAD_EBBRR(r3)
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std r0, THREAD_EBBRR(r3)
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/* PMU registers made user read/(write) by EBB */
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mfspr r0, SPRN_SIAR
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std r0, THREAD_SIAR(r3)
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mfspr r0, SPRN_SDAR
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std r0, THREAD_SDAR(r3)
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mfspr r0, SPRN_SIER
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std r0, THREAD_SIER(r3)
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mfspr r0, SPRN_MMCR0
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std r0, THREAD_MMCR0(r3)
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mfspr r0, SPRN_MMCR2
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std r0, THREAD_MMCR2(r3)
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mfspr r0, SPRN_MMCRA
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std r0, THREAD_MMCRA(r3)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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#endif
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#endif
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@ -581,20 +567,6 @@ BEGIN_FTR_SECTION
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ld r0, THREAD_EBBRR(r4)
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ld r0, THREAD_EBBRR(r4)
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mtspr SPRN_EBBRR, r0
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mtspr SPRN_EBBRR, r0
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/* PMU registers made user read/(write) by EBB */
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ld r0, THREAD_SIAR(r4)
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mtspr SPRN_SIAR, r0
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ld r0, THREAD_SDAR(r4)
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mtspr SPRN_SDAR, r0
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ld r0, THREAD_SIER(r4)
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mtspr SPRN_SIER, r0
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ld r0, THREAD_MMCR0(r4)
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mtspr SPRN_MMCR0, r0
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ld r0, THREAD_MMCR2(r4)
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mtspr SPRN_MMCR2, r0
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ld r0, THREAD_MMCRA(r4)
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mtspr SPRN_MMCRA, r0
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ld r0,THREAD_TAR(r4)
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ld r0,THREAD_TAR(r4)
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mtspr SPRN_TAR,r0
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mtspr SPRN_TAR,r0
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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@ -454,38 +454,14 @@ BEGIN_FTR_SECTION
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xori r10,r10,(MSR_FE0|MSR_FE1)
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xori r10,r10,(MSR_FE0|MSR_FE1)
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mtmsrd r10
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mtmsrd r10
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sync
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sync
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fmr 0,0
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fmr 1,1
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#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
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fmr 2,2
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#define FMR4(n) FMR2(n) ; FMR2(n+2)
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fmr 3,3
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#define FMR8(n) FMR4(n) ; FMR4(n+4)
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fmr 4,4
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#define FMR16(n) FMR8(n) ; FMR8(n+8)
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fmr 5,5
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#define FMR32(n) FMR16(n) ; FMR16(n+16)
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fmr 6,6
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FMR32(0)
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fmr 7,7
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fmr 8,8
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fmr 9,9
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fmr 10,10
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fmr 11,11
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fmr 12,12
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fmr 13,13
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fmr 14,14
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fmr 15,15
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fmr 16,16
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fmr 17,17
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fmr 18,18
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fmr 19,19
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fmr 20,20
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fmr 21,21
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fmr 22,22
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fmr 23,23
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fmr 24,24
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fmr 25,25
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fmr 26,26
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fmr 27,27
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fmr 28,28
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fmr 29,29
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fmr 30,30
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fmr 31,31
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FTR_SECTION_ELSE
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FTR_SECTION_ELSE
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/*
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/*
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* To denormalise we need to move a copy of the register to itself.
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* To denormalise we need to move a copy of the register to itself.
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@ -495,39 +471,25 @@ FTR_SECTION_ELSE
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oris r10,r10,MSR_VSX@h
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oris r10,r10,MSR_VSX@h
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mtmsrd r10
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mtmsrd r10
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sync
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sync
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XVCPSGNDP(0,0,0)
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XVCPSGNDP(1,1,1)
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#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
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XVCPSGNDP(2,2,2)
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#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
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XVCPSGNDP(3,3,3)
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#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
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XVCPSGNDP(4,4,4)
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#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
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XVCPSGNDP(5,5,5)
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#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
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XVCPSGNDP(6,6,6)
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XVCPSGNDP32(0)
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XVCPSGNDP(7,7,7)
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XVCPSGNDP(8,8,8)
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XVCPSGNDP(9,9,9)
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XVCPSGNDP(10,10,10)
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XVCPSGNDP(11,11,11)
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XVCPSGNDP(12,12,12)
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XVCPSGNDP(13,13,13)
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XVCPSGNDP(14,14,14)
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XVCPSGNDP(15,15,15)
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|
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XVCPSGNDP(16,16,16)
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XVCPSGNDP(17,17,17)
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XVCPSGNDP(18,18,18)
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|
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XVCPSGNDP(19,19,19)
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XVCPSGNDP(20,20,20)
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XVCPSGNDP(21,21,21)
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XVCPSGNDP(22,22,22)
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|
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XVCPSGNDP(23,23,23)
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|
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XVCPSGNDP(24,24,24)
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XVCPSGNDP(25,25,25)
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XVCPSGNDP(26,26,26)
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|
||||||
XVCPSGNDP(27,27,27)
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XVCPSGNDP(28,28,28)
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|
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XVCPSGNDP(29,29,29)
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|
||||||
XVCPSGNDP(30,30,30)
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|
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XVCPSGNDP(31,31,31)
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|
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ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
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ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
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||||||
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||||||
|
BEGIN_FTR_SECTION
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b denorm_done
|
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END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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/*
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||||||
|
* To denormalise we need to move a copy of the register to itself.
|
||||||
|
* For POWER8 we need to do that for all 64 VSX registers
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||||||
|
*/
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XVCPSGNDP32(32)
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denorm_done:
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mtspr SPRN_HSRR0,r11
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mtspr SPRN_HSRR0,r11
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mtcrf 0x80,r9
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mtcrf 0x80,r9
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ld r9,PACA_EXGEN+EX_R9(r13)
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ld r9,PACA_EXGEN+EX_R9(r13)
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||||||
|
|
|
@ -827,6 +827,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
|
||||||
}
|
}
|
||||||
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
||||||
struct resource *res = dev->resource + i;
|
struct resource *res = dev->resource + i;
|
||||||
|
struct pci_bus_region reg;
|
||||||
if (!res->flags)
|
if (!res->flags)
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
|
@ -835,8 +836,9 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
|
||||||
* at 0 as unset as well, except if PCI_PROBE_ONLY is also set
|
* at 0 as unset as well, except if PCI_PROBE_ONLY is also set
|
||||||
* since in that case, we don't want to re-assign anything
|
* since in that case, we don't want to re-assign anything
|
||||||
*/
|
*/
|
||||||
|
pcibios_resource_to_bus(dev, ®, res);
|
||||||
if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
|
if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
|
||||||
(res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
|
(reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
|
||||||
/* Only print message if not re-assigning */
|
/* Only print message if not re-assigning */
|
||||||
if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
|
if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
|
||||||
pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
|
pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
|
||||||
|
|
|
@ -399,7 +399,8 @@ static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
|
||||||
static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
|
static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
|
||||||
{
|
{
|
||||||
mtspr(SPRN_DABR, dabr);
|
mtspr(SPRN_DABR, dabr);
|
||||||
mtspr(SPRN_DABRX, dabrx);
|
if (cpu_has_feature(CPU_FTR_DABRX))
|
||||||
|
mtspr(SPRN_DABRX, dabrx);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
|
|
@ -1758,7 +1758,7 @@ static void perf_event_interrupt(struct pt_regs *regs)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if ((!found) && printk_ratelimit())
|
if (!found && !nmi && printk_ratelimit())
|
||||||
printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
|
printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -83,7 +83,11 @@ static int pseries_eeh_init(void)
|
||||||
ibm_configure_pe = rtas_token("ibm,configure-pe");
|
ibm_configure_pe = rtas_token("ibm,configure-pe");
|
||||||
ibm_configure_bridge = rtas_token("ibm,configure-bridge");
|
ibm_configure_bridge = rtas_token("ibm,configure-bridge");
|
||||||
|
|
||||||
/* necessary sanity check */
|
/*
|
||||||
|
* Necessary sanity check. We needn't check "get-config-addr-info"
|
||||||
|
* and its variant since the old firmware probably support address
|
||||||
|
* of domain/bus/slot/function for EEH RTAS operations.
|
||||||
|
*/
|
||||||
if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) {
|
if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) {
|
||||||
pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n",
|
pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n",
|
||||||
__func__);
|
__func__);
|
||||||
|
@ -102,12 +106,6 @@ static int pseries_eeh_init(void)
|
||||||
pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n",
|
pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n",
|
||||||
__func__);
|
__func__);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
} else if (ibm_get_config_addr_info2 == RTAS_UNKNOWN_SERVICE &&
|
|
||||||
ibm_get_config_addr_info == RTAS_UNKNOWN_SERVICE) {
|
|
||||||
pr_warning("%s: RTAS service <ibm,get-config-addr-info2> and "
|
|
||||||
"<ibm,get-config-addr-info> invalid\n",
|
|
||||||
__func__);
|
|
||||||
return -EINVAL;
|
|
||||||
} else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE &&
|
} else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE &&
|
||||||
ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) {
|
ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) {
|
||||||
pr_warning("%s: RTAS service <ibm,configure-pe> and "
|
pr_warning("%s: RTAS service <ibm,configure-pe> and "
|
||||||
|
|
Loading…
Reference in New Issue