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powerpc/8xx: mfspr SPRN_TBRx in lieu of mftb/mftbu is not supported 

Commit beb2dc0a7a breaks the MPC8xx which
seems to not support using mfspr SPRN_TBRx instead of mftb/mftbu
despite what is written in the reference manual.

This patch reverts to the use of mftb/mftbu when CONFIG_8xx is
selected.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
LEROY Christophe 2013-11-22 17:57:31 +01:00 committed by Scott Wood
parent cbf8a358be
commit ae2163be10
5 changed files with 37 additions and 0 deletions
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14
arch/powerpc/boot/util.S
View File

@ -71,18 +71,32 @@ udelay:
add r4,r4,r5 add r4,r4,r5
addi r4,r4,-1 addi r4,r4,-1
divw r4,r4,r5 /* BUS ticks */ divw r4,r4,r5 /* BUS ticks */
#ifdef CONFIG_8xx
1: mftbu r5
mftb r6
mftbu r7
#else
1: mfspr r5, SPRN_TBRU 1: mfspr r5, SPRN_TBRU
mfspr r6, SPRN_TBRL mfspr r6, SPRN_TBRL
mfspr r7, SPRN_TBRU mfspr r7, SPRN_TBRU
#endif
cmpw 0,r5,r7 cmpw 0,r5,r7
bne 1b /* Get [synced] base time */ bne 1b /* Get [synced] base time */
addc r9,r6,r4 /* Compute end time */ addc r9,r6,r4 /* Compute end time */
addze r8,r5 addze r8,r5
#ifdef CONFIG_8xx
2: mftbu r5
#else
2: mfspr r5, SPRN_TBRU 2: mfspr r5, SPRN_TBRU
#endif
cmpw 0,r5,r8 cmpw 0,r5,r8
blt 2b blt 2b
bgt 3f bgt 3f
#ifdef CONFIG_8xx
mftb r6
#else
mfspr r6, SPRN_TBRL mfspr r6, SPRN_TBRL
#endif
cmpw 0,r6,r9 cmpw 0,r6,r9
blt 2b blt 2b
3: blr 3: blr

2
arch/powerpc/include/asm/ppc_asm.h
View File

@ -366,6 +366,8 @@ BEGIN_FTR_SECTION_NESTED(96); \
cmpwi dest,0; \ cmpwi dest,0; \
beq- 90b; \ beq- 90b; \
END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
#elif defined(CONFIG_8xx)
#define MFTB(dest) mftb dest
#else #else
#define MFTB(dest) mfspr dest, SPRN_TBRL #define MFTB(dest) mfspr dest, SPRN_TBRL
#endif #endif

7
arch/powerpc/include/asm/reg.h
View File

@ -1174,12 +1174,19 @@
#else /* __powerpc64__ */ #else /* __powerpc64__ */
#if defined(CONFIG_8xx)
#define mftbl() ({unsigned long rval; \
asm volatile("mftbl %0" : "=r" (rval)); rval;})
#define mftbu() ({unsigned long rval; \
asm volatile("mftbu %0" : "=r" (rval)); rval;})
#else
#define mftbl() ({unsigned long rval; \ #define mftbl() ({unsigned long rval; \
asm volatile("mfspr %0, %1" : "=r" (rval) : \ asm volatile("mfspr %0, %1" : "=r" (rval) : \
"i" (SPRN_TBRL)); rval;}) "i" (SPRN_TBRL)); rval;})
#define mftbu() ({unsigned long rval; \ #define mftbu() ({unsigned long rval; \
asm volatile("mfspr %0, %1" : "=r" (rval) : \ asm volatile("mfspr %0, %1" : "=r" (rval) : \
"i" (SPRN_TBRU)); rval;}) "i" (SPRN_TBRU)); rval;})
#endif
#endif /* !__powerpc64__ */ #endif /* !__powerpc64__ */
#define mttbl(v) asm volatile("mttbl %0":: "r"(v)) #define mttbl(v) asm volatile("mttbl %0":: "r"(v))

8
arch/powerpc/include/asm/timex.h
View File

@ -29,7 +29,11 @@ static inline cycles_t get_cycles(void)
ret = 0; ret = 0;
__asm__ __volatile__( __asm__ __volatile__(
#ifdef CONFIG_8xx
"97: mftb %0\n"
#else
"97: mfspr %0, %2\n" "97: mfspr %0, %2\n"
#endif
"99:\n" "99:\n"
".section __ftr_fixup,\"a\"\n" ".section __ftr_fixup,\"a\"\n"
".align 2\n" ".align 2\n"
@ -41,7 +45,11 @@ static inline cycles_t get_cycles(void)
" .long 0\n" " .long 0\n"
" .long 0\n" " .long 0\n"
".previous" ".previous"
#ifdef CONFIG_8xx
: "=r" (ret) : "i" (CPU_FTR_601));
#else
: "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL)); : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
#endif
return ret; return ret;
#endif #endif
} }

6
arch/powerpc/kernel/vdso32/gettimeofday.S
View File

@ -232,9 +232,15 @@ __do_get_tspec:
lwz r6,(CFG_TB_ORIG_STAMP+4)(r9) lwz r6,(CFG_TB_ORIG_STAMP+4)(r9)
/* Get a stable TB value */ /* Get a stable TB value */
#ifdef CONFIG_8xx
2: mftbu r3
mftbl r4
mftbu r0
#else
2: mfspr r3, SPRN_TBRU 2: mfspr r3, SPRN_TBRU
mfspr r4, SPRN_TBRL mfspr r4, SPRN_TBRL
mfspr r0, SPRN_TBRU mfspr r0, SPRN_TBRU
#endif
cmplw cr0,r3,r0 cmplw cr0,r3,r0
bne- 2b bne- 2b