Merge MTD updates into -next
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commit
adf716d2f3
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@ -480,6 +480,42 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
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nand_writel(info, NDCR, ndcr | int_mask);
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}
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static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
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{
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if (info->ecc_bch) {
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int timeout;
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/*
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* According to the datasheet, when reading from NDDB
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* with BCH enabled, after each 32 bytes reads, we
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* have to make sure that the NDSR.RDDREQ bit is set.
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*
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* Drain the FIFO 8 32 bits reads at a time, and skip
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* the polling on the last read.
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*/
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while (len > 8) {
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__raw_readsl(info->mmio_base + NDDB, data, 8);
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for (timeout = 0;
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!(nand_readl(info, NDSR) & NDSR_RDDREQ);
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timeout++) {
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if (timeout >= 5) {
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dev_err(&info->pdev->dev,
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"Timeout on RDDREQ while draining the FIFO\n");
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return;
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}
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mdelay(1);
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}
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data += 32;
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len -= 8;
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}
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}
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__raw_readsl(info->mmio_base + NDDB, data, len);
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}
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static void handle_data_pio(struct pxa3xx_nand_info *info)
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{
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unsigned int do_bytes = min(info->data_size, info->chunk_size);
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@ -496,14 +532,14 @@ static void handle_data_pio(struct pxa3xx_nand_info *info)
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DIV_ROUND_UP(info->oob_size, 4));
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break;
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case STATE_PIO_READING:
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__raw_readsl(info->mmio_base + NDDB,
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info->data_buff + info->data_buff_pos,
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DIV_ROUND_UP(do_bytes, 4));
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drain_fifo(info,
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info->data_buff + info->data_buff_pos,
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DIV_ROUND_UP(do_bytes, 4));
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if (info->oob_size > 0)
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__raw_readsl(info->mmio_base + NDDB,
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info->oob_buff + info->oob_buff_pos,
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DIV_ROUND_UP(info->oob_size, 4));
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drain_fifo(info,
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info->oob_buff + info->oob_buff_pos,
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DIV_ROUND_UP(info->oob_size, 4));
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break;
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default:
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dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
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