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ARM: l2c: spear13xx: remove cache size override 

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2014-03-19 12:18:02 +00:00
parent 8b5c18f056
commit adf4b00ebf
1 changed files with 1 additions and 1 deletions
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arch/arm/mach-spear/spear13xx.c
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@ -46,7 +46,7 @@ void __init spear13xx_l2x0_init(void)
*/
writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
l2x0_init(VA_L2CC_BASE, 0x30a60001, 0xfe00ffff);
l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff);
}
/*