soc: bcm: brcmstb: biuctrl: Update programming for 7211
Add a matching entry for 7211 which can be programmed with the same BIUCTRL settings as other Brahma-B53 based SoCs. While at it, rename the function to include a72 in the name to reflect this applies to both types of 64-bit capable CPUs that we support (Brahma-B53 and Cortex-A72). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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@ -107,7 +107,8 @@ static int __init mcp_write_pairing_set(void)
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return 0;
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}
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static const u32 b53_mach_compat[] = {
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static const u32 a72_b53_mach_compat[] = {
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0x7211,
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0x7216,
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0x7255,
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0x7260,
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@ -116,19 +117,19 @@ static const u32 b53_mach_compat[] = {
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0x7278,
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};
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static void __init mcp_b53_set(void)
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static void __init mcp_a72_b53_set(void)
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{
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unsigned int i;
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u32 reg;
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reg = brcmstb_get_family_id();
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for (i = 0; i < ARRAY_SIZE(b53_mach_compat); i++) {
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if (BRCM_ID(reg) == b53_mach_compat[i])
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for (i = 0; i < ARRAY_SIZE(a72_b53_mach_compat); i++) {
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if (BRCM_ID(reg) == a72_b53_mach_compat[i])
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break;
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}
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if (i == ARRAY_SIZE(b53_mach_compat))
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if (i == ARRAY_SIZE(a72_b53_mach_compat))
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return;
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/* Set all 3 MCP interfaces to 8 credits */
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@ -261,7 +262,7 @@ static int __init brcmstb_biuctrl_init(void)
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return ret;
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}
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mcp_b53_set();
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mcp_a72_b53_set();
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#ifdef CONFIG_PM_SLEEP
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register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
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#endif
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