dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
Add DT binding documentation for WIZ (SERDES wrapper). WIZ is *NOT* a PHY but a wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) serdes. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [jsarha@ti.com: Add separate compatible for Sierra(16G) and Torrent(10G) SERDES] Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Rob Herring <robh@kernel.org>
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Kishon Vijay Abraham I
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: TI J721E WIZ (SERDES Wrapper)
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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properties:
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compatible:
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enum:
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- ti,j721e-wiz-16g
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- ti,j721e-wiz-10g
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power-domains:
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maxItems: 1
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clocks:
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maxItems: 3
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description: clock-specifier to represent input to the WIZ
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clock-names:
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items:
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- const: fck
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- const: core_ref_clk
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- const: ext_ref_clk
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num-lanes:
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minimum: 1
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maximum: 4
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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"#reset-cells":
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const: 1
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ranges: true
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assigned-clocks:
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maxItems: 2
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assigned-clock-parents:
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maxItems: 2
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patternProperties:
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"^pll[0|1]-refclk$":
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type: object
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description: |
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WIZ node should have subnodes for each of the PLLs present in
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the SERDES.
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properties:
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clocks:
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maxItems: 2
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description: Phandle to clock nodes representing the two inputs to PLL.
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"#clock-cells":
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const: 0
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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required:
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- clocks
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- "#clock-cells"
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- assigned-clocks
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- assigned-clock-parents
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"^cmn-refclk1?-dig-div$":
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type: object
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description:
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WIZ node should have subnodes for each of the PMA common refclock
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provided by the SERDES.
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properties:
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clocks:
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maxItems: 1
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description: Phandle to the clock node representing the input to the
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divider clock.
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"#clock-cells":
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const: 0
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required:
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- clocks
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- "#clock-cells"
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"^refclk-dig$":
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type: object
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description: |
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WIZ node should have subnode for refclk_dig to select the reference
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clock source for the reference clock used in the PHY and PMA digital
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logic.
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properties:
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clocks:
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maxItems: 4
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description: Phandle to four clock nodes representing the inputs to
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refclk_dig
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"#clock-cells":
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const: 0
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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required:
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- clocks
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- "#clock-cells"
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- assigned-clocks
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- assigned-clock-parents
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"^serdes@[0-9a-f]+$":
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type: object
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description: |
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WIZ node should have '1' subnode for the SERDES. It could be either
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Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
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bindings specified in
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Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
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Torrent SERDES should follow the bindings specified in
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Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
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required:
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- compatible
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- power-domains
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- clocks
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- clock-names
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- num-lanes
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- "#address-cells"
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- "#size-cells"
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- "#reset-cells"
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- ranges
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examples:
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- |
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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wiz@5000000 {
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compatible = "ti,j721e-wiz-16g";
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#address-cells = <1>;
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#size-cells = <1>;
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power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
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clock-names = "fck", "core_ref_clk", "ext_ref_clk";
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assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
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assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
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num-lanes = <2>;
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#reset-cells = <1>;
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ranges = <0x5000000 0x5000000 0x10000>;
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pll0-refclk {
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clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
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#clock-cells = <0>;
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assigned-clocks = <&wiz1_pll0_refclk>;
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assigned-clock-parents = <&k3_clks 293 13>;
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};
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pll1-refclk {
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clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
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#clock-cells = <0>;
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assigned-clocks = <&wiz1_pll1_refclk>;
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assigned-clock-parents = <&k3_clks 293 0>;
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};
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cmn-refclk-dig-div {
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clocks = <&wiz1_refclk_dig>;
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#clock-cells = <0>;
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};
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cmn-refclk1-dig-div {
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clocks = <&wiz1_pll1_refclk>;
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#clock-cells = <0>;
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};
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refclk-dig {
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clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
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#clock-cells = <0>;
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assigned-clocks = <&wiz0_refclk_dig>;
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assigned-clock-parents = <&k3_clks 292 11>;
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};
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serdes@5000000 {
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compatible = "cdns,ti,sierra-phy-t0";
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reg-names = "serdes";
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reg = <0x5000000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&serdes_wiz0 0>;
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reset-names = "sierra_reset";
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clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
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clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
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};
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};
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