clocksource: Add missing line break to error messages
Printing with pr_* functions requires adding line break manually. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
parent
9a4914ce0d
commit
ac9ce6d1a0
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@ -37,7 +37,7 @@ static int noinline arc_get_timer_clk(struct device_node *node)
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("timer missing clk");
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pr_err("timer missing clk\n");
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return PTR_ERR(clk);
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}
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@ -89,7 +89,7 @@ static int __init arc_cs_setup_gfrc(struct device_node *node)
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READ_BCR(ARC_REG_MCIP_BCR, mp);
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if (!mp.gfrc) {
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pr_warn("Global-64-bit-Ctr clocksource not detected");
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pr_warn("Global-64-bit-Ctr clocksource not detected\n");
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return -ENXIO;
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}
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@ -140,13 +140,13 @@ static int __init arc_cs_setup_rtc(struct device_node *node)
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READ_BCR(ARC_REG_TIMERS_BCR, timer);
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if (!timer.rtc) {
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pr_warn("Local-64-bit-Ctr clocksource not detected");
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pr_warn("Local-64-bit-Ctr clocksource not detected\n");
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return -ENXIO;
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}
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/* Local to CPU hence not usable in SMP */
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if (IS_ENABLED(CONFIG_SMP)) {
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pr_warn("Local-64-bit-Ctr not usable in SMP");
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pr_warn("Local-64-bit-Ctr not usable in SMP\n");
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return -EINVAL;
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}
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@ -290,13 +290,13 @@ static int __init arc_clockevent_setup(struct device_node *node)
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arc_timer_irq = irq_of_parse_and_map(node, 0);
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if (arc_timer_irq <= 0) {
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pr_err("clockevent: missing irq");
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pr_err("clockevent: missing irq\n");
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return -EINVAL;
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}
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ret = arc_get_timer_clk(node);
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if (ret) {
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pr_err("clockevent: missing clk");
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pr_err("clockevent: missing clk\n");
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return ret;
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}
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@ -313,7 +313,7 @@ static int __init arc_clockevent_setup(struct device_node *node)
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arc_timer_starting_cpu,
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arc_timer_dying_cpu);
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if (ret) {
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pr_err("Failed to setup hotplug state");
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pr_err("Failed to setup hotplug state\n");
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return ret;
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}
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return 0;
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@ -1055,7 +1055,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
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ret = -EINVAL;
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if (!irq) {
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pr_err("arch_timer: Frame missing %s irq",
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pr_err("arch_timer: Frame missing %s irq\n",
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arch_timer_mem_use_virtual ? "virt" : "phys");
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goto out;
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}
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@ -193,7 +193,7 @@ static int __init asm9260_timer_init(struct device_node *np)
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priv.base = of_io_request_and_map(np, 0, np->name);
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if (IS_ERR(priv.base)) {
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pr_err("%s: unable to map resource", np->name);
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pr_err("%s: unable to map resource\n", np->name);
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return PTR_ERR(priv.base);
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}
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@ -89,13 +89,13 @@ static int __init bcm2835_timer_init(struct device_node *node)
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("Can't remap registers");
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pr_err("Can't remap registers\n");
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return -ENXIO;
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}
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ret = of_property_read_u32(node, "clock-frequency", &freq);
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if (ret) {
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pr_err("Can't read clock-frequency");
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pr_err("Can't read clock-frequency\n");
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goto err_iounmap;
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}
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@ -107,7 +107,7 @@ static int __init bcm2835_timer_init(struct device_node *node)
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irq = irq_of_parse_and_map(node, DEFAULT_TIMER);
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if (irq <= 0) {
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pr_err("Can't parse IRQ");
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pr_err("Can't parse IRQ\n");
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ret = -EINVAL;
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goto err_iounmap;
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}
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@ -179,7 +179,7 @@ static int __init kona_timer_init(struct device_node *node)
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} else if (!of_property_read_u32(node, "clock-frequency", &freq)) {
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arch_timer_rate = freq;
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} else {
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pr_err("Kona Timer v1 unable to determine clock-frequency");
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pr_err("Kona Timer v1 unable to determine clock-frequency\n");
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return -EINVAL;
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}
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@ -40,7 +40,7 @@ void __init clocksource_probe(void)
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ret = init_func_ret(np);
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if (ret) {
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pr_err("Failed to initialize '%s': %d",
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pr_err("Failed to initialize '%s': %d\n",
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of_node_full_name(np), ret);
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continue;
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}
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@ -101,7 +101,7 @@ static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
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struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
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if (!evt->event_handler) {
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pr_info("Spurious APBT timer interrupt %d", irq);
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pr_info("Spurious APBT timer interrupt %d\n", irq);
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return IRQ_NONE;
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}
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@ -133,13 +133,13 @@ static int __init meson6_timer_init(struct device_node *node)
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timer_base = of_io_request_and_map(node, 0, "meson6-timer");
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if (IS_ERR(timer_base)) {
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pr_err("Can't map registers");
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pr_err("Can't map registers\n");
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return -ENXIO;
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}
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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pr_err("Can't parse IRQ");
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pr_err("Can't parse IRQ\n");
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return -EINVAL;
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}
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@ -174,7 +174,7 @@ static int __init gic_clocksource_of_init(struct device_node *node)
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if (!gic_present || !node->parent ||
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!of_device_is_compatible(node->parent, "mti,gic")) {
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pr_warn("No DT definition for the mips gic driver");
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pr_warn("No DT definition for the mips gic driver\n");
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return -ENXIO;
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}
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@ -260,25 +260,25 @@ static int __init nmdk_timer_of_init(struct device_node *node)
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("Can't remap registers");
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pr_err("Can't remap registers\n");
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return -ENXIO;
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}
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pclk = of_clk_get_by_name(node, "apb_pclk");
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if (IS_ERR(pclk)) {
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pr_err("could not get apb_pclk");
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pr_err("could not get apb_pclk\n");
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return PTR_ERR(pclk);
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}
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clk = of_clk_get_by_name(node, "timclk");
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if (IS_ERR(clk)) {
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pr_err("could not get timclk");
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pr_err("could not get timclk\n");
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return PTR_ERR(clk);
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}
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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pr_err("Can't parse IRQ");
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pr_err("Can't parse IRQ\n");
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return -EINVAL;
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}
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@ -166,14 +166,14 @@ static int __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
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ret = setup_irq(irq, &pxa_ost0_irq);
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if (ret) {
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pr_err("Failed to setup irq");
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pr_err("Failed to setup irq\n");
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return ret;
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}
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ret = clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200,
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32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("Failed to init clocksource");
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pr_err("Failed to init clocksource\n");
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return ret;
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}
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@ -203,7 +203,7 @@ static int __init pxa_timer_dt_init(struct device_node *np)
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_crit("Failed to prepare clock");
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pr_crit("Failed to prepare clock\n");
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return ret;
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}
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@ -385,7 +385,7 @@ static int __init _samsung_pwm_clocksource_init(void)
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mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
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channel = fls(mask) - 1;
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if (channel < 0) {
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pr_crit("failed to find PWM channel for clocksource");
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pr_crit("failed to find PWM channel for clocksource\n");
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return -EINVAL;
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}
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pwm.source_id = channel;
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@ -393,7 +393,7 @@ static int __init _samsung_pwm_clocksource_init(void)
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mask &= ~(1 << channel);
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channel = fls(mask) - 1;
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if (channel < 0) {
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pr_crit("failed to find PWM channel for clock event");
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pr_crit("failed to find PWM channel for clock event\n");
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return -EINVAL;
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}
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pwm.event_id = channel;
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@ -448,7 +448,7 @@ static int __init samsung_pwm_alloc(struct device_node *np,
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pwm.timerclk = of_clk_get_by_name(np, "timers");
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if (IS_ERR(pwm.timerclk)) {
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pr_crit("failed to get timers clock for timer");
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pr_crit("failed to get timers clock for timer\n");
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return PTR_ERR(pwm.timerclk);
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}
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@ -159,25 +159,25 @@ static int __init sun4i_timer_init(struct device_node *node)
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timer_base = of_iomap(node, 0);
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if (!timer_base) {
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pr_crit("Can't map registers");
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pr_crit("Can't map registers\n");
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return -ENXIO;
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}
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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pr_crit("Can't parse IRQ");
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pr_crit("Can't parse IRQ\n");
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return -EINVAL;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_crit("Can't get timer clock");
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pr_crit("Can't get timer clock\n");
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return PTR_ERR(clk);
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Failed to prepare clock");
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pr_err("Failed to prepare clock\n");
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return ret;
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}
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@ -200,7 +200,7 @@ static int __init sun4i_timer_init(struct device_node *node)
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ret = clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
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rate, 350, 32, clocksource_mmio_readl_down);
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if (ret) {
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pr_err("Failed to register clocksource");
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pr_err("Failed to register clocksource\n");
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return ret;
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}
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@ -245,7 +245,7 @@ static int __init tegra20_init_rtc(struct device_node *np)
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rtc_base = of_iomap(np, 0);
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if (!rtc_base) {
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pr_err("Can't map RTC registers");
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pr_err("Can't map RTC registers\n");
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return -ENXIO;
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}
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@ -247,13 +247,13 @@ static int __init armada_370_xp_timer_common_init(struct device_node *np)
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timer_base = of_iomap(np, 0);
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if (!timer_base) {
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pr_err("Failed to iomap");
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pr_err("Failed to iomap\n");
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return -ENXIO;
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}
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local_base = of_iomap(np, 1);
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if (!local_base) {
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pr_err("Failed to iomap");
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pr_err("Failed to iomap\n");
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return -ENXIO;
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}
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@ -298,7 +298,7 @@ static int __init armada_370_xp_timer_common_init(struct device_node *np)
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"armada_370_xp_clocksource",
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timer_clk, 300, 32, clocksource_mmio_readl_down);
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if (res) {
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pr_err("Failed to initialize clocksource mmio");
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pr_err("Failed to initialize clocksource mmio\n");
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return res;
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}
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@ -315,7 +315,7 @@ static int __init armada_370_xp_timer_common_init(struct device_node *np)
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armada_370_xp_evt);
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/* Immediately configure the timer on the boot CPU */
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if (res) {
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pr_err("Failed to request percpu irq");
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pr_err("Failed to request percpu irq\n");
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return res;
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}
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@ -324,7 +324,7 @@ static int __init armada_370_xp_timer_common_init(struct device_node *np)
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armada_370_xp_timer_starting_cpu,
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armada_370_xp_timer_dying_cpu);
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if (res) {
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pr_err("Failed to setup hotplug state and timer");
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pr_err("Failed to setup hotplug state and timer\n");
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return res;
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}
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@ -339,7 +339,7 @@ static int __init armada_xp_timer_init(struct device_node *np)
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int ret;
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if (IS_ERR(clk)) {
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pr_err("Failed to get clock");
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pr_err("Failed to get clock\n");
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return PTR_ERR(clk);
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}
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@ -375,7 +375,7 @@ static int __init armada_375_timer_init(struct device_node *np)
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/* Must have at least a clock */
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if (IS_ERR(clk)) {
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pr_err("Failed to get clock");
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pr_err("Failed to get clock\n");
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return PTR_ERR(clk);
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}
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@ -399,7 +399,7 @@ static int __init armada_370_timer_init(struct device_node *np)
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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pr_err("Failed to get clock");
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pr_err("Failed to get clock\n");
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return PTR_ERR(clk);
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}
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@ -235,7 +235,7 @@ static int __init efm32_clockevent_init(struct device_node *np)
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ret = setup_irq(irq, &efm32_clock_event_irq);
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if (ret) {
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pr_err("Failed setup irq");
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pr_err("Failed setup irq\n");
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goto err_setup_irq;
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}
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@ -141,7 +141,7 @@ static int __init orion_timer_init(struct device_node *np)
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Failed to prepare clock");
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pr_err("Failed to prepare clock\n");
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return ret;
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}
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@ -165,7 +165,7 @@ static int __init orion_timer_init(struct device_node *np)
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"orion_clocksource", rate, 300, 32,
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clocksource_mmio_readl_down);
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if (ret) {
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pr_err("Failed to initialize mmio timer");
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pr_err("Failed to initialize mmio timer\n");
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return ret;
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}
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@ -226,7 +226,7 @@ static int __init at91sam926x_pit_dt_init(struct device_node *node)
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ret = clocksource_register_hz(&data->clksrc, pit_rate);
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if (ret) {
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pr_err("Failed to register clocksource");
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pr_err("Failed to register clocksource\n");
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return ret;
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}
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@ -161,19 +161,19 @@ static int __init digicolor_timer_init(struct device_node *node)
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*/
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dc_timer_dev.base = of_iomap(node, 0);
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if (!dc_timer_dev.base) {
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pr_err("Can't map registers");
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pr_err("Can't map registers\n");
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return -ENXIO;
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}
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irq = irq_of_parse_and_map(node, dc_timer_dev.timer_id);
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if (irq <= 0) {
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pr_err("Can't parse IRQ");
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pr_err("Can't parse IRQ\n");
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return -EINVAL;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("Can't get timer clock");
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pr_err("Can't get timer clock\n");
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return PTR_ERR(clk);
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}
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clk_prepare_enable(clk);
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@ -200,7 +200,7 @@ static int __init integrator_ap_timer_init_of(struct device_node *node)
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err = of_property_read_string(of_aliases,
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"arm,timer-primary", &path);
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if (err) {
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pr_warn("Failed to read property");
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pr_warn("Failed to read property\n");
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return err;
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}
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@ -209,7 +209,7 @@ static int __init integrator_ap_timer_init_of(struct device_node *node)
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err = of_property_read_string(of_aliases,
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"arm,timer-secondary", &path);
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if (err) {
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pr_warn("Failed to read property");
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pr_warn("Failed to read property\n");
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return err;
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}
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|
|
|
@ -55,7 +55,7 @@ static int __init nps_get_timer_clk(struct device_node *node,
|
|||
*clk = of_clk_get(node, 0);
|
||||
ret = PTR_ERR_OR_ZERO(*clk);
|
||||
if (ret) {
|
||||
pr_err("timer missing clk");
|
||||
pr_err("timer missing clk\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -247,7 +247,7 @@ static int __init nps_setup_clockevent(struct device_node *node)
|
|||
|
||||
nps_timer0_irq = irq_of_parse_and_map(node, 0);
|
||||
if (nps_timer0_irq <= 0) {
|
||||
pr_err("clockevent: missing irq");
|
||||
pr_err("clockevent: missing irq\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -270,7 +270,7 @@ static int __init nps_setup_clockevent(struct device_node *node)
|
|||
nps_timer_starting_cpu,
|
||||
nps_timer_dying_cpu);
|
||||
if (ret) {
|
||||
pr_err("Failed to setup hotplug state");
|
||||
pr_err("Failed to setup hotplug state\n");
|
||||
clk_disable_unprepare(clk);
|
||||
free_percpu_irq(nps_timer0_irq, &nps_clockevent_device);
|
||||
return ret;
|
||||
|
|
|
@ -196,20 +196,20 @@ static int __init sirfsoc_prima2_timer_init(struct device_node *np)
|
|||
|
||||
clk = of_clk_get(np, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Failed to get clock");
|
||||
pr_err("Failed to get clock\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret) {
|
||||
pr_err("Failed to enable clock");
|
||||
pr_err("Failed to enable clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
rate = clk_get_rate(clk);
|
||||
|
||||
if (rate < PRIMA2_CLOCK_FREQ || rate % PRIMA2_CLOCK_FREQ) {
|
||||
pr_err("Invalid clock rate");
|
||||
pr_err("Invalid clock rate\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -229,7 +229,7 @@ static int __init sirfsoc_prima2_timer_init(struct device_node *np)
|
|||
|
||||
ret = clocksource_register_hz(&sirfsoc_clocksource, PRIMA2_CLOCK_FREQ);
|
||||
if (ret) {
|
||||
pr_err("Failed to register clocksource");
|
||||
pr_err("Failed to register clocksource\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -237,7 +237,7 @@ static int __init sirfsoc_prima2_timer_init(struct device_node *np)
|
|||
|
||||
ret = setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
|
||||
if (ret) {
|
||||
pr_err("Failed to setup irq");
|
||||
pr_err("Failed to setup irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
@ -299,13 +299,13 @@ static int __init integrator_cp_of_init(struct device_node *np)
|
|||
|
||||
base = of_iomap(np, 0);
|
||||
if (!base) {
|
||||
pr_err("Failed to iomap");
|
||||
pr_err("Failed to iomap\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
clk = of_clk_get(np, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Failed to get clock");
|
||||
pr_err("Failed to get clock\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
|
|
|
@ -332,19 +332,19 @@ static int __init sun5i_timer_init(struct device_node *node)
|
|||
|
||||
timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
|
||||
if (IS_ERR(timer_base)) {
|
||||
pr_err("Can't map registers");
|
||||
pr_err("Can't map registers\n");
|
||||
return PTR_ERR(timer_base);;
|
||||
}
|
||||
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
if (irq <= 0) {
|
||||
pr_err("Can't parse IRQ");
|
||||
pr_err("Can't parse IRQ\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
clk = of_clk_get(node, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Can't get timer clock");
|
||||
pr_err("Can't get timer clock\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
|
|
|
@ -165,7 +165,7 @@ static int __init pit_timer_init(struct device_node *np)
|
|||
|
||||
timer_base = of_iomap(np, 0);
|
||||
if (!timer_base) {
|
||||
pr_err("Failed to iomap");
|
||||
pr_err("Failed to iomap\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue