reset: Add i.MX7 SRC reset driver
Add reset controller driver exposing various reset faculties, implemented by System Reset Controller IP block. Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Andrey Smirnov
Philipp Zabel
parent
d518d9cab1
commit
abf97755ae
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@ -0,0 +1,47 @@
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Freescale i.MX7 System Reset Controller
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======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "fsl,imx7-src", "syscon"
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain SRC interrupt
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- #reset-cells: 1, see below
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example:
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src: reset-controller@30390000 {
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compatible = "fsl,imx7d-src", "syscon";
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reg = <0x30390000 0x2000>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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The system reset controller can be used to reset various set of
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peripherals. Device nodes that need access to reset lines should
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specify them as a reset phandle in their corresponding node as
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specified in reset.txt.
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Example:
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pcie: pcie@33800000 {
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...
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resets = <&src IMX7_RESET_PCIEPHY>,
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<&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
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reset-names = "pciephy", "apps";
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...
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};
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For list of all valid reset indicies see
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<dt-bindings/reset/imx7-reset.h>
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@ -27,6 +27,13 @@ config RESET_BERLIN
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help
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This enables the reset controller driver for Marvell Berlin SoCs.
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config RESET_IMX7
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bool "i.MX7 Reset Driver" if COMPILE_TEST
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default SOC_IMX7D
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select MFD_SYSCON
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help
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This enables the reset controller driver for i.MX7 SoCs.
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config RESET_LPC18XX
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bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
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default ARCH_LPC18XX
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@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
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obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
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obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
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obj-$(CONFIG_RESET_MESON) += reset-meson.o
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obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
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@ -15,3 +16,4 @@ obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o
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obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
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@ -0,0 +1,158 @@
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/*
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* Copyright (c) 2017, Impinj, Inc.
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*
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* i.MX7 System Reset Controller (SRC) driver
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/regmap.h>
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#include <dt-bindings/reset/imx7-reset.h>
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struct imx7_src {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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};
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enum imx7_src_registers {
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SRC_A7RCR0 = 0x0004,
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SRC_M4RCR = 0x000c,
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SRC_ERCR = 0x0014,
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SRC_HSICPHY_RCR = 0x001c,
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SRC_USBOPHY1_RCR = 0x0020,
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SRC_USBOPHY2_RCR = 0x0024,
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SRC_MIPIPHY_RCR = 0x0028,
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SRC_PCIEPHY_RCR = 0x002c,
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SRC_DDRC_RCR = 0x1000,
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};
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struct imx7_src_signal {
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unsigned int offset, bit;
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};
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static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
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[IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
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[IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
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[IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) },
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[IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
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[IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) },
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[IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) },
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[IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) },
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[IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) },
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[IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) },
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[IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) },
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[IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) },
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[IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) },
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[IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) },
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[IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) },
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[IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) },
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[IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) },
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[IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) },
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[IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) },
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[IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) },
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[IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) },
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[IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
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[IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
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[IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
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[IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) },
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[IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
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};
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static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct imx7_src, rcdev);
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}
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static int imx7_reset_set(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct imx7_src *imx7src = to_imx7_src(rcdev);
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const struct imx7_src_signal *signal = &imx7_src_signals[id];
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unsigned int value = 0;
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switch (id) {
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case IMX7_RESET_PCIEPHY:
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/*
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* wait for more than 10us to release phy g_rst and
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* btnrst
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*/
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if (!assert)
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udelay(10);
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break;
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case IMX7_RESET_PCIE_CTRL_APPS_EN:
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value = (assert) ? 0 : signal->bit;
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break;
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}
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return regmap_update_bits(imx7src->regmap,
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signal->offset, signal->bit, value);
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}
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static int imx7_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx7_reset_set(rcdev, id, true);
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}
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static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return imx7_reset_set(rcdev, id, false);
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}
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static const struct reset_control_ops imx7_reset_ops = {
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.assert = imx7_reset_assert,
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.deassert = imx7_reset_deassert,
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};
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static int imx7_reset_probe(struct platform_device *pdev)
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{
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struct imx7_src *imx7src;
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struct device *dev = &pdev->dev;
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struct regmap_config config = { .name = "src" };
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imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
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if (!imx7src)
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return -ENOMEM;
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imx7src->regmap = syscon_node_to_regmap(dev->of_node);
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if (IS_ERR(imx7src->regmap)) {
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dev_err(dev, "Unable to get imx7-src regmap");
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return PTR_ERR(imx7src->regmap);
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}
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regmap_attach_dev(dev, imx7src->regmap, &config);
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imx7src->rcdev.owner = THIS_MODULE;
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imx7src->rcdev.nr_resets = IMX7_RESET_NUM;
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imx7src->rcdev.ops = &imx7_reset_ops;
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imx7src->rcdev.of_node = dev->of_node;
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return devm_reset_controller_register(dev, &imx7src->rcdev);
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}
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static const struct of_device_id imx7_reset_dt_ids[] = {
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{ .compatible = "fsl,imx7d-src", },
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{ /* sentinel */ },
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};
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static struct platform_driver imx7_reset_driver = {
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.probe = imx7_reset_probe,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = imx7_reset_dt_ids,
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},
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};
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builtin_platform_driver(imx7_reset_driver);
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@ -0,0 +1,62 @@
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/*
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* Copyright (C) 2017 Impinj, Inc.
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef DT_BINDING_RESET_IMX7_H
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#define DT_BINDING_RESET_IMX7_H
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#define IMX7_RESET_A7_CORE_POR_RESET0 0
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#define IMX7_RESET_A7_CORE_POR_RESET1 1
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#define IMX7_RESET_A7_CORE_RESET0 2
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#define IMX7_RESET_A7_CORE_RESET1 3
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#define IMX7_RESET_A7_DBG_RESET0 4
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#define IMX7_RESET_A7_DBG_RESET1 5
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#define IMX7_RESET_A7_ETM_RESET0 6
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#define IMX7_RESET_A7_ETM_RESET1 7
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#define IMX7_RESET_A7_SOC_DBG_RESET 8
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#define IMX7_RESET_A7_L2RESET 9
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#define IMX7_RESET_SW_M4C_RST 10
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#define IMX7_RESET_SW_M4P_RST 11
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#define IMX7_RESET_EIM_RST 12
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#define IMX7_RESET_HSICPHY_PORT_RST 13
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#define IMX7_RESET_USBPHY1_POR 14
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#define IMX7_RESET_USBPHY1_PORT_RST 15
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#define IMX7_RESET_USBPHY2_POR 16
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#define IMX7_RESET_USBPHY2_PORT_RST 17
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#define IMX7_RESET_MIPI_PHY_MRST 18
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#define IMX7_RESET_MIPI_PHY_SRST 19
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/*
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* IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
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* and PCIEPHY_G_RST
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*/
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#define IMX7_RESET_PCIEPHY 20
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#define IMX7_RESET_PCIEPHY_PERST 21
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/*
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* IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
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* can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
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* of as one
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*/
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#define IMX7_RESET_PCIE_CTRL_APPS_EN 22
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#define IMX7_RESET_DDRC_PRST 23
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#define IMX7_RESET_DDRC_CORE_RST 24
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#define IMX7_RESET_NUM 25
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#endif
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