Device tree changes for omaps for v4.8 merge window:
- PWM binding updates and related dts changes - OCM RAM updates for dra7 - Enable n900 lirc-rx51 driver - omap3-gta04 updates for backlight, bma180, itg3200, hmc5843 and wifi - am335x, am437x and am57xx operating point updates and additions - am335x-icev2 pca9536 node - dra72-evm regulator updates - edma spelling fixes - am335x and am437x ethernet phy update - a series of mcbsp updates - omap3-gta04 eeprom - dra7 PCIe unit address fix - stdout-path for beaglebone variants - crypto accelerator nodes for am335x, am437x and dra7 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXam0sAAoJEBvUPslcq6VzYewP/imm4it6lqwtsfNthtmSW/Qi PO6XyZ/j8ayRcddsrnjTPFLH8/fPaIkKxI2eCQZpe+rHhK6Ifg2lGrZonJS7pHmu 6NqRe0OkUHw3EIRuHW0uP4OCzYnyinJf0A7jp1nuQq5CBH8rzqHS7xyNEBryeKMQ rScauNPU+Z+/LM0Qz2mpYAAwWnJHlT/K8Pok+JoB16TiHsiNbhXoQlSwB1bDe+b6 5Ssz42AG68rp9dGJ8SnbY25qBwQc1oBZeE21ItHTMwfUlAeQiG4nxejzqYaPISQw Aj/5Q0+qYp8aiCbQXaYrt0+Tz7UBfFTK3xIuw3011P48SaJAVbTe3tjPbZuORZng RvUHtavk2hEAoHQfU9gRYFPHt9uNLZqGU8gTmILLL/Go9oPENeQeOmEPPMtDC2eu nBOa1ROsAsXPBKTWJrpDRCaH7i5W4md4U9mo8LCG2iCXVrPHXXnWoRWGiUchiMzm ykPK9ynL+CwQ6M5dHFhW4rsnDZdrG2v5YAVDdhLnCnl9MrIFINTNLA/6Axz+xq4/ 8B+ymUyW9ymrxeoxEQpCbFWHg3UfN0B97r1JUy1D8wDdfberGHM35FspkESEjEeP PYOcrk0zx1wbVOBhEthvwInPX72T870xyDyCgl7Y2ayp6upTMQXL6C3uK4DR4W1p TO/qrewNdyK5iA+FWtYr =2xdp -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.8/dt-part1-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Device tree changes for omaps for v4.8 merge window: - PWM binding updates and related dts changes - OCM RAM updates for dra7 - Enable n900 lirc-rx51 driver - omap3-gta04 updates for backlight, bma180, itg3200, hmc5843 and wifi - am335x, am437x and am57xx operating point updates and additions - am335x-icev2 pca9536 node - dra72-evm regulator updates - edma spelling fixes - am335x and am437x ethernet phy update - a series of mcbsp updates - omap3-gta04 eeprom - dra7 PCIe unit address fix - stdout-path for beaglebone variants - crypto accelerator nodes for am335x, am437x and dra7 * tag 'omap-for-v4.8/dt-part1-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (42 commits) ARM: dts: AM43xx: Add node for RNG ARM: dts: AM43xx: clk: Add RNG clk node ARM: dts: DRA7: Add DT node for RNG IP ARM: dts: DRA7: Add support for SHA IP ARM: dts: DRA7: Add DT nodes for AES IP ARM: dts: DRA7: Add DT node for DES IP ARM: dts: am335x-bone-common: use stdout-path in Beaglebone boards. ARM: dts: DRA7: fix unit address of second PCIe instance ARM: dts: omap3-gta04: Add RFID eeprom node ARM: dts: omap4-duovero: Add pdmclk binding for audio ARM: dts: omap4-var-som-om44: Add pdmclk binding for audio ARM: dts: omap4-sdp: Add pdmclk binding for audio ARM: dts: omap4-panda-common: Add pdmclk binding for audio ARM: dts: omap5-board-common: Add pdmclk binding for audio ARM: dts: omap3: Add clocks to McBSP nodes ARM: dts: am335x-bone-common: Mark MAC as having only one PHY ARM: dts: am437x-idk-evm: Mark MAC as having only one PHY ARM: dts: Correct misspelling, "emda3" -> "edma3" ARM: dts: dra72-evm: Rename 3.3V regulator tag ARM: dts: am335x-icev2: Add DT node for TI PCA9536 ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
abda5334d2
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@ -15,7 +15,7 @@ Required properties:
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- reg: Memory map of eDMA CC
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- reg-names: "edma3_cc"
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- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
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- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint"
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- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
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- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
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<&tptc_phandle TC_priority_number>. The highest priority is 0.
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@ -48,7 +48,7 @@ edma: edma@49000000 {
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reg = <0x49000000 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <12 13 14>;
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interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint";
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interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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@ -2,28 +2,48 @@ TI SOC ECAP based APWM controller
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Required properties:
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- compatible: Must be "ti,<soc>-ecap".
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for am33xx - compatible = "ti,am33xx-ecap";
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for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap";
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for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
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for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
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for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
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for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";
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- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
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the cells format. The PWM channel index ranges from 0 to 4. The only third
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cell flag supported by this binding is PWM_POLARITY_INVERTED.
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- reg: physical base address and size of the registers map.
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Optional properties:
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- ti,hwmods: Name of the hwmod associated to the ECAP:
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"ecap<x>", <x> being the 0-based instance number from the HW spec
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- clocks: Handle to the ECAP's functional clock.
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- clock-names: Must be set to "fck".
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Example:
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ecap0: ecap@0 { /* ECAP on am33xx */
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compatible = "ti,am33xx-ecap";
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ecap0: ecap@48300100 { /* ECAP on am33xx */
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compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
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#pwm-cells = <3>;
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reg = <0x48300100 0x80>;
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clocks = <&l4ls_gclk>;
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clock-names = "fck";
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};
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ecap0: ecap@48300100 { /* ECAP on am4372 */
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compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
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#pwm-cells = <3>;
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reg = <0x48300100 0x80>;
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ti,hwmods = "ecap0";
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clocks = <&l4ls_gclk>;
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clock-names = "fck";
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};
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ecap0: ecap@0 { /* ECAP on da850 */
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compatible = "ti,da850-ecap", "ti,am33xx-ecap";
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ecap0: ecap@1f06000 { /* ECAP on da850 */
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compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
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#pwm-cells = <3>;
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reg = <0x306000 0x80>;
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reg = <0x1f06000 0x80>;
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};
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ecap0: ecap@4843e100 {
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compatible = "ti,dra746-ecap", "ti,am3352-ecap";
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#pwm-cells = <3>;
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reg = <0x4843e100 0x80>;
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clocks = <&l4_root_clk_div>;
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clock-names = "fck";
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};
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@ -2,28 +2,48 @@ TI SOC EHRPWM based PWM controller
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Required properties:
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- compatible: Must be "ti,<soc>-ehrpwm".
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for am33xx - compatible = "ti,am33xx-ehrpwm";
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for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
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for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
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for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
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for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
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for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm";
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- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
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the cells format. The only third cell flag supported by this binding is
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PWM_POLARITY_INVERTED.
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- reg: physical base address and size of the registers map.
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Optional properties:
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- ti,hwmods: Name of the hwmod associated to the EHRPWM:
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"ehrpwm<x>", <x> being the 0-based instance number from the HW spec
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- clocks: Handle to the PWM's time-base and functional clock.
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- clock-names: Must be set to "tbclk" and "fck".
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Example:
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ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */
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compatible = "ti,am33xx-ehrpwm";
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ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
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compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x48300200 0x100>;
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clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
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clock-names = "tbclk", "fck";
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};
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ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */
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compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x48300200 0x80>;
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clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
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clock-names = "tbclk", "fck";
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ti,hwmods = "ehrpwm0";
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};
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ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */
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compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
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ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */
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compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x300000 0x2000>;
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reg = <0x1f00000 0x2000>;
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};
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ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */
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compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x4843e200 0x80>;
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clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
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clock-names = "tbclk", "fck";
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};
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@ -1,7 +1,11 @@
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TI SOC based PWM Subsystem
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Required properties:
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- compatible: Must be "ti,am33xx-pwmss";
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- compatible: Must be "ti,<soc>-pwmss".
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for am33xx - compatible = "ti,am33xx-pwmss";
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for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
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for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"
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- reg: physical base address and size of the registers map.
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- address-cells: Specify the number of u32 entries needed in child nodes.
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Should set to 1.
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@ -16,7 +20,7 @@ Required properties:
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Also child nodes should also populated under PWMSS DT node.
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Example:
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pwmss0: pwmss@48300000 {
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epwmss0: epwmss@48300000 { /* PWMSS for am33xx */
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compatible = "ti,am33xx-pwmss";
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reg = <0x48300000 0x10>;
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ti,hwmods = "epwmss0";
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@ -29,3 +33,28 @@ pwmss0: pwmss@48300000 {
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/* child nodes go here */
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};
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epwmss0: epwmss@48300000 { /* PWMSS for am4372 */
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compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"
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reg = <0x48300000 0x10>;
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ti,hwmods = "epwmss0";
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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ranges = <0x48300100 0x48300100 0x80 /* ECAP */
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0x48300180 0x48300180 0x80 /* EQEP */
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0x48300200 0x48300200 0x80>; /* EHRPWM */
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/* child nodes go here */
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};
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epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */
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compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
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reg = <0x4843e000 0x30>;
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ti,hwmods = "epwmss0";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* child nodes go here */
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};
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@ -18,6 +18,10 @@
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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chosen {
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stdout-path = &uart0;
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};
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leds {
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pinctrl-names = "default";
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pinctrl-0 = <&user_leds_s0>;
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@ -318,7 +322,7 @@
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/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
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regulator-name = "vdd_mpu";
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regulator-min-microvolt = <925000>;
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regulator-max-microvolt = <1325000>;
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regulator-max-microvolt = <1351500>;
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regulator-boot-on;
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regulator-always-on;
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};
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@ -359,12 +363,8 @@
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phy-mode = "mii";
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};
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&cpsw_emac1 {
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phy_id = <&davinci_mdio>, <1>;
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phy-mode = "mii";
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};
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&mac {
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slaves = <1>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&cpsw_default>;
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pinctrl-1 = <&cpsw_sleep>;
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@ -33,6 +33,17 @@
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status = "okay";
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};
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&cpu0_opp_table {
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/*
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* All PG 2.0 silicon may not support 1GHz but some of the early
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* BeagleBone Blacks have PG 2.0 silicon which is guaranteed
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* to support 1GHz OPP so enable it for PG 2.0 on this board.
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*/
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oppnitro@1000000000 {
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opp-supported-hw = <0x06 0x0100>;
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};
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};
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&am33xx_pinmux {
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nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
|
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pinctrl-single,pins = <
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|
|
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@ -640,7 +640,7 @@
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/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
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regulator-name = "vdd_mpu";
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regulator-min-microvolt = <912500>;
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regulator-max-microvolt = <1312500>;
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regulator-max-microvolt = <1351500>;
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regulator-boot-on;
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regulator-always-on;
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};
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|
|
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|
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@ -560,7 +560,7 @@
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/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
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regulator-name = "vdd_mpu";
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regulator-min-microvolt = <912500>;
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regulator-max-microvolt = <1312500>;
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regulator-max-microvolt = <1351500>;
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regulator-boot-on;
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regulator-always-on;
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};
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|
|
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|||
|
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@ -206,6 +206,13 @@
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|||
gpio-controller;
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||||
#gpio-cells = <2>;
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};
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|
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pca9536: gpio@41 {
|
||||
compatible = "ti,pca9536";
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reg = <0x41>;
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gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
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|
|
|
|||
|
|
@ -45,19 +45,9 @@
|
|||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
|
||||
/*
|
||||
* To consider voltage drop between PMIC and SoC,
|
||||
* tolerance value is reduced to 2% from 4% and
|
||||
* voltage value is increased as a precaution.
|
||||
*/
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
720000 1285000
|
||||
600000 1225000
|
||||
500000 1125000
|
||||
275000 1125000
|
||||
>;
|
||||
voltage-tolerance = <2>; /* 2 percentage */
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
|
||||
ti,syscon-rev = <&scm_conf 0x600>;
|
||||
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
|
@ -66,6 +56,78 @@
|
|||
};
|
||||
};
|
||||
|
||||
cpu0_opp_table: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
/*
|
||||
* The three following nodes are marked with opp-suspend
|
||||
* because the can not be enabled simultaneously on a
|
||||
* single SoC.
|
||||
*/
|
||||
opp50@300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <950000 931000 969000>;
|
||||
opp-supported-hw = <0x06 0x0010>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp100@275000000 {
|
||||
opp-hz = /bits/ 64 <275000000>;
|
||||
opp-microvolt = <1100000 1078000 1122000>;
|
||||
opp-supported-hw = <0x01 0x00FF>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp100@300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <1100000 1078000 1122000>;
|
||||
opp-supported-hw = <0x06 0x0020>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp100@500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <1100000 1078000 1122000>;
|
||||
opp-supported-hw = <0x01 0xFFFF>;
|
||||
};
|
||||
|
||||
opp100@600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1100000 1078000 1122000>;
|
||||
opp-supported-hw = <0x06 0x0040>;
|
||||
};
|
||||
|
||||
opp120@600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1200000 1176000 1224000>;
|
||||
opp-supported-hw = <0x01 0xFFFF>;
|
||||
};
|
||||
|
||||
opp120@720000000 {
|
||||
opp-hz = /bits/ 64 <720000000>;
|
||||
opp-microvolt = <1200000 1176000 1224000>;
|
||||
opp-supported-hw = <0x06 0x0080>;
|
||||
};
|
||||
|
||||
oppturbo@720000000 {
|
||||
opp-hz = /bits/ 64 <720000000>;
|
||||
opp-microvolt = <1260000 1234800 1285200>;
|
||||
opp-supported-hw = <0x01 0xFFFF>;
|
||||
};
|
||||
|
||||
oppturbo@800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1260000 1234800 1285200>;
|
||||
opp-supported-hw = <0x06 0x0100>;
|
||||
};
|
||||
|
||||
oppnitro@1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <1325000 1298500 1351500>;
|
||||
opp-supported-hw = <0x04 0x0200>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a8-pmu";
|
||||
interrupts = <3>;
|
||||
|
|
@ -187,7 +249,7 @@
|
|||
reg = <0x49000000 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "emda3_mperr",
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
|
@ -679,20 +741,24 @@
|
|||
0x48300200 0x48300200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap0: ecap@48300100 {
|
||||
compatible = "ti,am33xx-ecap";
|
||||
compatible = "ti,am3352-ecap",
|
||||
"ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300100 0x80>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
interrupts = <31>;
|
||||
interrupt-names = "ecap0";
|
||||
ti,hwmods = "ecap0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm0: pwm@48300200 {
|
||||
compatible = "ti,am33xx-ehrpwm";
|
||||
compatible = "ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300200 0x80>;
|
||||
ti,hwmods = "ehrpwm0";
|
||||
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -709,20 +775,24 @@
|
|||
0x48302200 0x48302200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap1: ecap@48302100 {
|
||||
compatible = "ti,am33xx-ecap";
|
||||
compatible = "ti,am3352-ecap",
|
||||
"ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302100 0x80>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
interrupts = <47>;
|
||||
interrupt-names = "ecap1";
|
||||
ti,hwmods = "ecap1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm1: pwm@48302200 {
|
||||
compatible = "ti,am33xx-ehrpwm";
|
||||
compatible = "ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302200 0x80>;
|
||||
ti,hwmods = "ehrpwm1";
|
||||
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -739,20 +809,24 @@
|
|||
0x48304200 0x48304200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap2: ecap@48304100 {
|
||||
compatible = "ti,am33xx-ecap";
|
||||
compatible = "ti,am3352-ecap",
|
||||
"ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304100 0x80>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
interrupts = <61>;
|
||||
interrupt-names = "ecap2";
|
||||
ti,hwmods = "ecap2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm2: pwm@48304200 {
|
||||
compatible = "ti,am33xx-ehrpwm";
|
||||
compatible = "ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304200 0x80>;
|
||||
ti,hwmods = "ehrpwm2";
|
||||
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -44,10 +44,49 @@
|
|||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>;
|
||||
ti,syscon-rev = <&scm_conf 0x600>;
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
};
|
||||
};
|
||||
|
||||
cpu0_opp_table: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp50@300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <950000 931000 969000>;
|
||||
opp-supported-hw = <0xFF 0x01>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp100@600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1100000 1078000 1122000>;
|
||||
opp-supported-hw = <0xFF 0x04>;
|
||||
};
|
||||
|
||||
opp120@720000000 {
|
||||
opp-hz = /bits/ 64 <720000000>;
|
||||
opp-microvolt = <1200000 1176000 1224000>;
|
||||
opp-supported-hw = <0xFF 0x08>;
|
||||
};
|
||||
|
||||
oppturbo@800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1260000 1234800 1285200>;
|
||||
opp-supported-hw = <0xFF 0x10>;
|
||||
};
|
||||
|
||||
oppnitro@1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <1325000 1298500 1351500>;
|
||||
opp-supported-hw = <0xFF 0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@48241000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
|
|
@ -199,7 +238,7 @@
|
|||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_ccint", "emda3_mperr",
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
|
@ -672,18 +711,24 @@
|
|||
status = "disabled";
|
||||
|
||||
ecap0: ecap@48300100 {
|
||||
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
||||
compatible = "ti,am4372-ecap",
|
||||
"ti,am3352-ecap",
|
||||
"ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300100 0x80>;
|
||||
ti,hwmods = "ecap0";
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm0: pwm@48300200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
compatible = "ti,am4372-ehrpwm",
|
||||
"ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300200 0x80>;
|
||||
ti,hwmods = "ehrpwm0";
|
||||
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -698,18 +743,24 @@
|
|||
status = "disabled";
|
||||
|
||||
ecap1: ecap@48302100 {
|
||||
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
||||
compatible = "ti,am4372-ecap",
|
||||
"ti,am3352-ecap",
|
||||
"ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302100 0x80>;
|
||||
ti,hwmods = "ecap1";
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm1: pwm@48302200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
compatible = "ti,am4372-ehrpwm",
|
||||
"ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302200 0x80>;
|
||||
ti,hwmods = "ehrpwm1";
|
||||
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -724,18 +775,24 @@
|
|||
status = "disabled";
|
||||
|
||||
ecap2: ecap@48304100 {
|
||||
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
||||
compatible = "ti,am4372-ecap",
|
||||
"ti,am3352-ecap",
|
||||
"ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304100 0x80>;
|
||||
ti,hwmods = "ecap2";
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm2: pwm@48304200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
compatible = "ti,am4372-ehrpwm",
|
||||
"ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304200 0x80>;
|
||||
ti,hwmods = "ehrpwm2";
|
||||
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -750,10 +807,13 @@
|
|||
status = "disabled";
|
||||
|
||||
ehrpwm3: pwm@48306200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
compatible = "ti,am4372-ehrpwm",
|
||||
"ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48306200 0x80>;
|
||||
ti,hwmods = "ehrpwm3";
|
||||
clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -768,10 +828,13 @@
|
|||
status = "disabled";
|
||||
|
||||
ehrpwm4: pwm@48308200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
compatible = "ti,am4372-ehrpwm",
|
||||
"ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48308200 0x80>;
|
||||
ti,hwmods = "ehrpwm4";
|
||||
clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -786,10 +849,13 @@
|
|||
status = "disabled";
|
||||
|
||||
ehrpwm5: pwm@4830a200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
compatible = "ti,am4372-ehrpwm",
|
||||
"ti,am3352-ehrpwm",
|
||||
"ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x4830a200 0x80>;
|
||||
ti,hwmods = "ehrpwm5";
|
||||
clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -843,6 +909,13 @@
|
|||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
rng: rng@48310000 {
|
||||
compatible = "ti,omap4-rng";
|
||||
ti,hwmods = "rng";
|
||||
reg = <0x48310000 0x2000>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
mcasp0: mcasp@48038000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
ti,hwmods = "mcasp0";
|
||||
|
|
|
|||
|
|
@ -975,3 +975,7 @@
|
|||
clock-names = "ext-clk", "int-clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu {
|
||||
cpu0-supply = <&dcdc2>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -382,6 +382,7 @@
|
|||
};
|
||||
|
||||
&mac {
|
||||
slaves = <1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
|
|
|
|||
|
|
@ -104,6 +104,14 @@
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
rng_fck: rng_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
|
|
|
|||
|
|
@ -448,7 +448,7 @@
|
|||
reg = <0x49000000 0x10000>;
|
||||
reg-names = "edma3_cc";
|
||||
interrupts = <12 13 14>;
|
||||
interrupt-names = "edma3_ccint", "emda3_mperr",
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -73,6 +73,49 @@
|
|||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>;
|
||||
ti,syscon-rev = <&scm_wkup 0x204>;
|
||||
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
|
||||
/* cooling options */
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <2>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
};
|
||||
|
||||
cpu0_opp_table: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp_nom@1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <1060000 850000 1150000>;
|
||||
opp-supported-hw = <0xFF 0x01>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp_od@1176000000 {
|
||||
opp-hz = /bits/ 64 <1176000000>;
|
||||
opp-microvolt = <1160000 885000 1160000>;
|
||||
opp-supported-hw = <0xFF 0x02>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
|
|
@ -233,6 +276,11 @@
|
|||
prm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scm_wkup: scm_conf@c000 {
|
||||
compatible = "syscon";
|
||||
reg = <0xc000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
axi@0 {
|
||||
|
|
@ -276,7 +324,7 @@
|
|||
ranges = <0x51800000 0x51800000 0x3000
|
||||
0x0 0x30000000 0x10000000>;
|
||||
status = "disabled";
|
||||
pcie@51000000 {
|
||||
pcie@51800000 {
|
||||
compatible = "ti,dra7-pcie";
|
||||
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
|
||||
reg-names = "rc_dbics", "ti_conf", "config";
|
||||
|
|
@ -304,6 +352,53 @@
|
|||
};
|
||||
};
|
||||
|
||||
ocmcram1: ocmcram@40300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40300000 0x80000>;
|
||||
ranges = <0x0 0x40300000 0x80000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* This is a placeholder for an optional reserved
|
||||
* region for use by secure software. The size
|
||||
* of this region is not known until runtime so it
|
||||
* is set as zero to either be updated to reserve
|
||||
* space or left unchanged to leave all SRAM for use.
|
||||
* On HS parts that that require the reserved region
|
||||
* either the bootloader can update the size to
|
||||
* the required amount or the node can be overridden
|
||||
* from the board dts file for the secure platform.
|
||||
*/
|
||||
sram-hs@0 {
|
||||
compatible = "ti,secure-ram";
|
||||
reg = <0x0 0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* NOTE: ocmcram2 and ocmcram3 are not available on all
|
||||
* DRA7xx and AM57xx variants. Confirm availability in
|
||||
* the data manual for the exact part number in use
|
||||
* before enabling these nodes in the board dts file.
|
||||
*/
|
||||
ocmcram2: ocmcram@40400000 {
|
||||
status = "disabled";
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40400000 0x100000>;
|
||||
ranges = <0x0 0x40400000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
ocmcram3: ocmcram@40500000 {
|
||||
status = "disabled";
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40500000 0x100000>;
|
||||
ranges = <0x0 0x40500000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
bandgap: bandgap@4a0021e0 {
|
||||
reg = <0x4a0021e0 0xc
|
||||
0x4a00232c 0xc
|
||||
|
|
@ -341,7 +436,7 @@
|
|||
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma3_ccint", "emda3_mperr",
|
||||
interrupt-names = "edma3_ccint", "edma3_mperr",
|
||||
"edma3_ccerrint";
|
||||
dma-requests = <64>;
|
||||
#dma-cells = <2>;
|
||||
|
|
@ -1743,6 +1838,149 @@
|
|||
clock-names = "fck", "sys_clk";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss0: epwmss@4843e000 {
|
||||
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
|
||||
reg = <0x4843e000 0x30>;
|
||||
ti,hwmods = "epwmss0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges;
|
||||
|
||||
ehrpwm0: pwm@4843e200 {
|
||||
compatible = "ti,dra746-ehrpwm",
|
||||
"ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x4843e200 0x80>;
|
||||
clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap0: ecap@4843e100 {
|
||||
compatible = "ti,dra746-ecap",
|
||||
"ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x4843e100 0x80>;
|
||||
clocks = <&l4_root_clk_div>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss1: epwmss@48440000 {
|
||||
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
|
||||
reg = <0x48440000 0x30>;
|
||||
ti,hwmods = "epwmss1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges;
|
||||
|
||||
ehrpwm1: pwm@48440200 {
|
||||
compatible = "ti,dra746-ehrpwm",
|
||||
"ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48440200 0x80>;
|
||||
clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap1: ecap@48440100 {
|
||||
compatible = "ti,dra746-ecap",
|
||||
"ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48440100 0x80>;
|
||||
clocks = <&l4_root_clk_div>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss2: epwmss@48442000 {
|
||||
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
|
||||
reg = <0x48442000 0x30>;
|
||||
ti,hwmods = "epwmss2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges;
|
||||
|
||||
ehrpwm2: pwm@48442200 {
|
||||
compatible = "ti,dra746-ehrpwm",
|
||||
"ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48442200 0x80>;
|
||||
clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
|
||||
clock-names = "tbclk", "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecap2: ecap@48442100 {
|
||||
compatible = "ti,dra746-ecap",
|
||||
"ti,am3352-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48442100 0x80>;
|
||||
clocks = <&l4_root_clk_div>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aes1: aes@4b500000 {
|
||||
compatible = "ti,omap4-aes";
|
||||
ti,hwmods = "aes1";
|
||||
reg = <0x4b500000 0xa0>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&l3_iclk_div>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
aes2: aes@4b700000 {
|
||||
compatible = "ti,omap4-aes";
|
||||
ti,hwmods = "aes2";
|
||||
reg = <0x4b700000 0xa0>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&l3_iclk_div>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
des: des@480a5000 {
|
||||
compatible = "ti,omap4-des";
|
||||
ti,hwmods = "des";
|
||||
reg = <0x480a5000 0xa0>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&l3_iclk_div>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
sham: sham@53100000 {
|
||||
compatible = "ti,omap5-sham";
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x4b101000 0x300>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&edma_xbar 119 0>;
|
||||
dma-names = "rx";
|
||||
clocks = <&l3_iclk_div>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
rng: rng@48090000 {
|
||||
compatible = "ti,omap4-rng";
|
||||
ti,hwmods = "rng";
|
||||
reg = <0x48090000 0x2000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&l3_iclk_div>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
display0 = &hdmi0;
|
||||
};
|
||||
|
||||
evm_3v3: fixedregulator-evm_3v3 {
|
||||
evm_3v3_sw: fixedregulator-evm_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "evm_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
/* TPS77018DBVT */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "aic_dvdd";
|
||||
vin-supply = <&evm_3v3>;
|
||||
vin-supply = <&evm_3v3_sw>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
|
@ -414,9 +414,9 @@
|
|||
status = "okay";
|
||||
|
||||
/* Regulators */
|
||||
AVDD-supply = <&evm_3v3>;
|
||||
IOVDD-supply = <&evm_3v3>;
|
||||
DRVDD-supply = <&evm_3v3>;
|
||||
AVDD-supply = <&evm_3v3_sw>;
|
||||
IOVDD-supply = <&evm_3v3_sw>;
|
||||
DRVDD-supply = <&evm_3v3_sw>;
|
||||
DVDD-supply = <&aic_dvdd>;
|
||||
};
|
||||
};
|
||||
|
|
@ -597,7 +597,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins_default>;
|
||||
|
||||
vmmc-supply = <&evm_3v3>;
|
||||
vmmc-supply = <&evm_3v3_sw>;
|
||||
bus-width = <8>;
|
||||
ti,non-removable;
|
||||
max-frequency = <192000000>;
|
||||
|
|
|
|||
|
|
@ -12,22 +12,6 @@
|
|||
/ {
|
||||
compatible = "ti,dra722", "ti,dra72", "ti,dra7";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
|
||||
/* cooling options */
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <2>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupt-parent = <&wakeupgen>;
|
||||
|
|
|
|||
|
|
@ -13,34 +13,11 @@
|
|||
compatible = "ti,dra742", "ti,dra74", "ti,dra7";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0>;
|
||||
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1000000 1060000
|
||||
1176000 1160000
|
||||
>;
|
||||
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
|
||||
/* cooling options */
|
||||
cooling-min-level = <0>;
|
||||
cooling-max-level = <2>;
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <1>;
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -100,6 +100,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm11 0 2000000 0>;
|
||||
pwm-names = "backlight";
|
||||
brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>;
|
||||
default-brightness-level = <9>; /* => 90 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&backlight_pins>;
|
||||
};
|
||||
|
||||
pwm11: dmtimer-pwm@11 {
|
||||
compatible = "ti,omap-dmtimer-pwm";
|
||||
ti,timers = <&timer11>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
hsusb2_phy: hsusb2_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
|
|
@ -139,6 +155,11 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
wifi_pwrseq: wifi_pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>; /* W2CBW003 reset through tca6507 */
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
|
|
@ -190,6 +211,12 @@
|
|||
>;
|
||||
};
|
||||
|
||||
backlight_pins: backlight_pins_pimnux {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3) /* gpt11/gpio57 */
|
||||
>;
|
||||
};
|
||||
|
||||
dss_dpi_pins: pinmux_dss_dpi_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
|
||||
|
|
@ -228,6 +255,24 @@
|
|||
OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */
|
||||
>;
|
||||
};
|
||||
|
||||
bma180_pins: pinmux_bma180_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */
|
||||
>;
|
||||
};
|
||||
|
||||
itg3200_pins: pinmux_itg3200_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */
|
||||
>;
|
||||
};
|
||||
|
||||
hmc5843_pins: pinmux_hmc5843_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core2 {
|
||||
|
|
@ -298,6 +343,8 @@
|
|||
bma180@41 {
|
||||
compatible = "bosch,bma180";
|
||||
reg = <0x41>;
|
||||
pinctrl-names = "default";
|
||||
pintcrl-0 = <&bma180_pins>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */
|
||||
};
|
||||
|
|
@ -306,12 +353,14 @@
|
|||
itg3200@68 {
|
||||
compatible = "invensense,itg3200";
|
||||
reg = <0x68>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&itg3200_pins>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <24 0>; /* GPIO_56 */
|
||||
interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */
|
||||
};
|
||||
|
||||
/* leds */
|
||||
tca6507@45 {
|
||||
/* leds + gpios */
|
||||
tca6507: tca6507@45 {
|
||||
compatible = "ti,tca6507";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -351,6 +400,10 @@
|
|||
hmc5843@1e {
|
||||
compatible = "honeywell,hmc5883l";
|
||||
reg = <0x1e>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hmc5843_pins>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* gpio112 */
|
||||
};
|
||||
|
||||
/* touchscreen */
|
||||
|
|
@ -362,6 +415,12 @@
|
|||
gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;
|
||||
ti,x-plate-ohms = <600>;
|
||||
};
|
||||
|
||||
/* RFID EEPROM */
|
||||
m24lr64@50 {
|
||||
compatible = "at,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
|
|
@ -398,6 +457,7 @@
|
|||
bus-width = <4>;
|
||||
ti,non-removable;
|
||||
cap-power-off-card;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
|
|
|
|||
|
|
@ -143,6 +143,18 @@
|
|||
io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
|
||||
io-channel-names = "temp", "bsi", "vbat";
|
||||
};
|
||||
|
||||
pwm9: dmtimer-pwm@9 {
|
||||
compatible = "ti,omap-dmtimer-pwm";
|
||||
#pwm-cells = <3>;
|
||||
ti,timers = <&timer9>;
|
||||
ti,clock-source = <0x00>; /* timer_sys_ck */
|
||||
};
|
||||
|
||||
ir: n900-ir {
|
||||
compatible = "nokia,n900-ir";
|
||||
pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
|
|
|
|||
|
|
@ -493,6 +493,8 @@
|
|||
dmas = <&sdma 31>,
|
||||
<&sdma 32>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&mcbsp1_fck>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -511,6 +513,8 @@
|
|||
dmas = <&sdma 33>,
|
||||
<&sdma 34>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
|
||||
clock-names = "fck", "ick";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -529,6 +533,8 @@
|
|||
dmas = <&sdma 17>,
|
||||
<&sdma 18>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
|
||||
clock-names = "fck", "ick";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -545,6 +551,8 @@
|
|||
dmas = <&sdma 19>,
|
||||
<&sdma 20>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&mcbsp4_fck>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -561,6 +569,8 @@
|
|||
dmas = <&sdma 21>,
|
||||
<&sdma 22>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&mcbsp5_fck>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -177,6 +177,7 @@
|
|||
|
||||
twl6040: twl@4b {
|
||||
compatible = "ti,twl6040";
|
||||
#clock-cells = <0>;
|
||||
reg = <0x4b>;
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
|
||||
ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* gpio_160 */
|
||||
|
|
@ -207,6 +208,10 @@
|
|||
&mcpdm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcpdm_pins>;
|
||||
|
||||
clocks = <&twl6040>;
|
||||
clock-names = "pdmclk";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -376,6 +376,7 @@
|
|||
|
||||
twl6040: twl@4b {
|
||||
compatible = "ti,twl6040";
|
||||
#clock-cells = <0>;
|
||||
reg = <0x4b>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -479,6 +480,10 @@
|
|||
&mcpdm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcpdm_pins>;
|
||||
|
||||
clocks = <&twl6040>;
|
||||
clock-names = "pdmclk";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -367,6 +367,7 @@
|
|||
|
||||
twl6040: twl@4b {
|
||||
compatible = "ti,twl6040";
|
||||
#clock-cells = <0>;
|
||||
reg = <0x4b>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -620,6 +621,10 @@
|
|||
&mcpdm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcpdm_pins>;
|
||||
|
||||
clocks = <&twl6040>;
|
||||
clock-names = "pdmclk";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -189,6 +189,7 @@
|
|||
|
||||
twl6040: twl@4b {
|
||||
compatible = "ti,twl6040";
|
||||
#clock-cells = <0>;
|
||||
reg = <0x4b>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -252,6 +253,10 @@
|
|||
&mcpdm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcpdm_pins>;
|
||||
|
||||
clocks = <&twl6040>;
|
||||
clock-names = "pdmclk";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -594,6 +594,7 @@
|
|||
|
||||
twl6040: twl@4b {
|
||||
compatible = "ti,twl6040";
|
||||
#clock-cells = <0>;
|
||||
reg = <0x4b>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -614,6 +615,10 @@
|
|||
&mcpdm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcpdm_pins>;
|
||||
|
||||
clocks = <&twl6040>;
|
||||
clock-names = "pdmclk";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ static struct ti_dt_clk am43xx_clks[] = {
|
|||
DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
|
||||
DT_CLK(NULL, "sha0_fck", "sha0_fck"),
|
||||
DT_CLK(NULL, "aes0_fck", "aes0_fck"),
|
||||
DT_CLK(NULL, "rng_fck", "rng_fck"),
|
||||
DT_CLK(NULL, "timer1_fck", "timer1_fck"),
|
||||
DT_CLK(NULL, "timer2_fck", "timer2_fck"),
|
||||
DT_CLK(NULL, "timer3_fck", "timer3_fck"),
|
||||
|
|
|
|||
Loading…
Reference in New Issue