[media] em28xx: add support for PLEX PX-BCUD (ISDB-S)
PX-BCUD has the following components: USB interface: Empia EM28178 Demodulator: Toshiba TC90532 (works by code for TC90522) Tuner: Next version of Sharp QM1D1C0042 em28xx_dvb_init(): add init code for PLEX PX-BCUD with calling px_bcud_init() that does things like pin configuration. qm1d1c0042_init(): support the next version of QM1D1C0042, change to choose an appropriate array of initial registers by reading chip id. [mchehab@osg.samsung.com: fold a fixup patch and fix checkpatch.pl errors/warnings, where applicable] Signed-off-by: Satoshi Nagahama <sattnag@aim.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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7977a15ede
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ab4d14528f
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@ -32,14 +32,24 @@
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#include "qm1d1c0042.h"
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#define QM1D1C0042_NUM_REGS 0x20
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#define QM1D1C0042_NUM_REG_ROWS 2
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static const u8 reg_initval[QM1D1C0042_NUM_REGS] = {
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static const u8
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reg_initval[QM1D1C0042_NUM_REG_ROWS][QM1D1C0042_NUM_REGS] = { {
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0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33,
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0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
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0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86,
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0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00
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}, {
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0x68, 0x1c, 0xc0, 0x10, 0xbc, 0xc1, 0x11, 0x33,
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0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
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0x00, 0xff, 0xf3, 0x00, 0x3f, 0x25, 0x5c, 0xd6,
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0x55, 0xcf, 0x95, 0xf6, 0x36, 0xf2, 0x09, 0x00
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}
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};
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static int reg_index;
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static const struct qm1d1c0042_config default_cfg = {
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.xtal_freq = 16000,
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.lpf = 1,
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@ -320,7 +330,6 @@ static int qm1d1c0042_init(struct dvb_frontend *fe)
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int i, ret;
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state = fe->tuner_priv;
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memcpy(state->regs, reg_initval, sizeof(reg_initval));
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reg_write(state, 0x01, 0x0c);
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reg_write(state, 0x01, 0x0c);
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@ -330,15 +339,22 @@ static int qm1d1c0042_init(struct dvb_frontend *fe)
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goto failed;
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usleep_range(2000, 3000);
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val = state->regs[0x01] | 0x10;
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ret = reg_write(state, 0x01, val); /* soft reset off */
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ret = reg_write(state, 0x01, 0x1c); /* soft reset off */
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if (ret < 0)
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goto failed;
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/* check ID */
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/* check ID and choose initial registers corresponding ID */
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ret = reg_read(state, 0x00, &val);
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if (ret < 0 || val != 0x48)
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if (ret < 0)
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goto failed;
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for (reg_index = 0; reg_index < QM1D1C0042_NUM_REG_ROWS;
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reg_index++) {
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if (val == reg_initval[reg_index][0x00])
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break;
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}
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if (reg_index >= QM1D1C0042_NUM_REG_ROWS)
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goto failed;
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memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS);
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usleep_range(2000, 3000);
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state->regs[0x0c] |= 0x40;
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@ -59,6 +59,8 @@ config VIDEO_EM28XX_DVB
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select DVB_DRX39XYJ if MEDIA_SUBDRV_AUTOSELECT
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select DVB_SI2168 if MEDIA_SUBDRV_AUTOSELECT
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select MEDIA_TUNER_SI2157 if MEDIA_SUBDRV_AUTOSELECT
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select DVB_TC90522 if MEDIA_SUBDRV_AUTOSELECT
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select MEDIA_TUNER_QM1D1C0042 if MEDIA_SUBDRV_AUTOSELECT
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---help---
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This adds support for DVB cards based on the
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Empiatech em28xx chips.
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@ -492,6 +492,20 @@ static struct em28xx_reg_seq terratec_t2_stick_hd[] = {
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{-1, -1, -1, -1},
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};
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static struct em28xx_reg_seq plex_px_bcud[] = {
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{EM2874_R80_GPIO_P0_CTRL, 0xff, 0xff, 0},
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{0x0d, 0xff, 0xff, 0},
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{EM2874_R50_IR_CONFIG, 0x01, 0xff, 0},
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{EM28XX_R06_I2C_CLK, 0x40, 0xff, 0},
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{EM2874_R80_GPIO_P0_CTRL, 0xfd, 0xff, 100},
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{EM28XX_R12_VINENABLE, 0x20, 0x20, 0},
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{0x0d, 0x42, 0xff, 1000},
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{EM2874_R80_GPIO_P0_CTRL, 0xfc, 0xff, 10},
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{EM2874_R80_GPIO_P0_CTRL, 0xfd, 0xff, 10},
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{0x73, 0xfd, 0xff, 100},
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{-1, -1, -1, -1},
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};
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/*
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* Button definitions
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*/
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@ -2306,6 +2320,20 @@ struct em28xx_board em28xx_boards[] = {
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.has_dvb = 1,
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.ir_codes = RC_MAP_TERRATEC_SLIM_2,
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},
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/*
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* 3275:0085 PLEX PX-BCUD.
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* Empia EM28178, TOSHIBA TC90532XBG, Sharp QM1D1C0042
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*/
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[EM28178_BOARD_PLEX_PX_BCUD] = {
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.name = "PLEX PX-BCUD",
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.xclk = EM28XX_XCLK_FREQUENCY_4_3MHZ,
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.def_i2c_bus = 1,
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.i2c_speed = EM28XX_I2C_CLK_WAIT_ENABLE,
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.tuner_type = TUNER_ABSENT,
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.tuner_gpio = plex_px_bcud,
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.has_dvb = 1,
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},
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};
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EXPORT_SYMBOL_GPL(em28xx_boards);
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@ -2495,6 +2523,8 @@ struct usb_device_id em28xx_id_table[] = {
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.driver_info = EM2861_BOARD_LEADTEK_VC100 },
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{ USB_DEVICE(0xeb1a, 0x8179),
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.driver_info = EM28178_BOARD_TERRATEC_T2_STICK_HD },
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{ USB_DEVICE(0x3275, 0x0085),
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.driver_info = EM28178_BOARD_PLEX_PX_BCUD },
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{ },
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};
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MODULE_DEVICE_TABLE(usb, em28xx_id_table);
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@ -58,6 +58,8 @@
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#include "ts2020.h"
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#include "si2168.h"
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#include "si2157.h"
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#include "tc90522.h"
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#include "qm1d1c0042.h"
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MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@infradead.org>");
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MODULE_LICENSE("GPL");
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@ -787,6 +789,68 @@ static int em28xx_mt352_terratec_xs_init(struct dvb_frontend *fe)
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return 0;
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}
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static void px_bcud_init(struct em28xx *dev)
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{
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int i;
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struct {
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unsigned char r[4];
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int len;
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} regs1[] = {
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{{ 0x0e, 0x77 }, 2},
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{{ 0x0f, 0x77 }, 2},
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{{ 0x03, 0x90 }, 2},
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}, regs2[] = {
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{{ 0x07, 0x01 }, 2},
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{{ 0x08, 0x10 }, 2},
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{{ 0x13, 0x00 }, 2},
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{{ 0x17, 0x00 }, 2},
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{{ 0x03, 0x01 }, 2},
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{{ 0x10, 0xb1 }, 2},
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{{ 0x11, 0x40 }, 2},
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{{ 0x85, 0x7a }, 2},
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{{ 0x87, 0x04 }, 2},
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};
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static struct em28xx_reg_seq gpio[] = {
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{EM28XX_R06_I2C_CLK, 0x40, 0xff, 300},
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{EM2874_R80_GPIO_P0_CTRL, 0xfd, 0xff, 60},
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{EM28XX_R15_RGAIN, 0x20, 0xff, 0},
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{EM28XX_R16_GGAIN, 0x20, 0xff, 0},
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{EM28XX_R17_BGAIN, 0x20, 0xff, 0},
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{EM28XX_R18_ROFFSET, 0x00, 0xff, 0},
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{EM28XX_R19_GOFFSET, 0x00, 0xff, 0},
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{EM28XX_R1A_BOFFSET, 0x00, 0xff, 0},
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{EM28XX_R23_UOFFSET, 0x00, 0xff, 0},
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{EM28XX_R24_VOFFSET, 0x00, 0xff, 0},
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{EM28XX_R26_COMPR, 0x00, 0xff, 0},
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{0x13, 0x08, 0xff, 0},
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{EM28XX_R12_VINENABLE, 0x27, 0xff, 0},
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{EM28XX_R0C_USBSUSP, 0x10, 0xff, 0},
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{EM28XX_R27_OUTFMT, 0x00, 0xff, 0},
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{EM28XX_R10_VINMODE, 0x00, 0xff, 0},
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{EM28XX_R11_VINCTRL, 0x11, 0xff, 0},
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{EM2874_R50_IR_CONFIG, 0x01, 0xff, 0},
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{EM2874_R5F_TS_ENABLE, 0x80, 0xff, 0},
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{EM28XX_R06_I2C_CLK, 0x46, 0xff, 0},
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};
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK, 0x46);
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/* sleeping ISDB-T */
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dev->dvb->i2c_client_demod->addr = 0x14;
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for (i = 0; i < ARRAY_SIZE(regs1); i++)
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i2c_master_send(dev->dvb->i2c_client_demod, regs1[i].r,
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regs1[i].len);
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/* sleeping ISDB-S */
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dev->dvb->i2c_client_demod->addr = 0x15;
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for (i = 0; i < ARRAY_SIZE(regs2); i++)
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i2c_master_send(dev->dvb->i2c_client_demod, regs2[i].r,
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regs2[i].len);
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for (i = 0; i < ARRAY_SIZE(gpio); i++) {
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em28xx_write_reg_bits(dev, gpio[i].reg, gpio[i].val,
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gpio[i].mask);
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if (gpio[i].sleep > 0)
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msleep(gpio[i].sleep);
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}
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};
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static struct mt352_config terratec_xs_mt352_cfg = {
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.demod_address = (0x1e >> 1),
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.no_tuner = 1,
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@ -1762,6 +1826,63 @@ static int em28xx_dvb_init(struct em28xx *dev)
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dvb->i2c_client_tuner = client;
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}
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break;
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case EM28178_BOARD_PLEX_PX_BCUD:
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{
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struct i2c_client *client;
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struct i2c_board_info info;
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struct tc90522_config tc90522_config;
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struct qm1d1c0042_config qm1d1c0042_config;
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/* attach demod */
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memset(&tc90522_config, 0, sizeof(tc90522_config));
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memset(&info, 0, sizeof(struct i2c_board_info));
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strlcpy(info.type, "tc90522sat", I2C_NAME_SIZE);
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info.addr = 0x15;
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info.platform_data = &tc90522_config;
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request_module("tc90522");
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client = i2c_new_device(&dev->i2c_adap[dev->def_i2c_bus], &info);
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if (client == NULL || client->dev.driver == NULL) {
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result = -ENODEV;
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goto out_free;
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}
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dvb->i2c_client_demod = client;
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if (!try_module_get(client->dev.driver->owner)) {
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i2c_unregister_device(client);
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result = -ENODEV;
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goto out_free;
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}
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/* attach tuner */
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memset(&qm1d1c0042_config, 0,
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sizeof(qm1d1c0042_config));
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qm1d1c0042_config.fe = tc90522_config.fe;
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qm1d1c0042_config.lpf = 1;
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memset(&info, 0, sizeof(struct i2c_board_info));
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strlcpy(info.type, "qm1d1c0042", I2C_NAME_SIZE);
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info.addr = 0x61;
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info.platform_data = &qm1d1c0042_config;
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request_module(info.type);
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client = i2c_new_device(tc90522_config.tuner_i2c,
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&info);
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if (client == NULL || client->dev.driver == NULL) {
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module_put(dvb->i2c_client_demod->dev.driver->owner);
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i2c_unregister_device(dvb->i2c_client_demod);
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result = -ENODEV;
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goto out_free;
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}
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dvb->i2c_client_tuner = client;
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if (!try_module_get(client->dev.driver->owner)) {
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i2c_unregister_device(client);
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module_put(dvb->i2c_client_demod->dev.driver->owner);
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i2c_unregister_device(dvb->i2c_client_demod);
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result = -ENODEV;
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goto out_free;
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}
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dvb->fe[0] = tc90522_config.fe;
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px_bcud_init(dev);
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}
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break;
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default:
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em28xx_errdev("/2: The frontend of your DVB/ATSC card"
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" isn't supported yet\n");
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@ -145,6 +145,7 @@
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#define EM2861_BOARD_LEADTEK_VC100 95
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#define EM28178_BOARD_TERRATEC_T2_STICK_HD 96
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#define EM2884_BOARD_ELGATO_EYETV_HYBRID_2008 97
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#define EM28178_BOARD_PLEX_PX_BCUD 98
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/* Limits minimum and default number of buffers */
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#define EM28XX_MIN_BUF 4
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