[POWERPC] Added indirect_type to handle variants of PCI ops
The generic PCI config ops indirect support for ppc32 covers only two cases (implicit vs explicit) type 0/1 config cycles via set_cfg_type. Added a indirect_type bit mask to handle other variants. Added support for PCI-e extended registers and moved the cfg_type handling into the bit mask for ARCH=powerpc. We can also use this to handle indirect quirks. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -33,22 +33,27 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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struct pci_controller *hose = bus->sysdata;
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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volatile void __iomem *cfg_data;
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u8 cfg_type = 0;
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u8 cfg_type = 0;
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u32 bus_no;
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u32 bus_no, reg;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->set_cfg_type)
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if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
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if (bus->number != hose->first_busno)
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if (bus->number != hose->first_busno)
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cfg_type = 1;
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cfg_type = 1;
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bus_no = (bus->number == hose->first_busno) ?
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bus_no = (bus->number == hose->first_busno) ?
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hose->self_busno : bus->number;
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hose->self_busno : bus->number;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
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reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
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else
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reg = offset & 0xfc;
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PCI_CFG_OUT(hose->cfg_addr,
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | (bus_no << 16)
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(0x80000000 | (bus_no << 16)
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| (devfn << 8) | ((offset & 0xfc) | cfg_type)));
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| (devfn << 8) | reg | cfg_type));
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/*
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/*
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* Note: the caller has already checked that offset is
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* Note: the caller has already checked that offset is
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@ -76,22 +81,27 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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struct pci_controller *hose = bus->sysdata;
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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volatile void __iomem *cfg_data;
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u8 cfg_type = 0;
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u8 cfg_type = 0;
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u32 bus_no;
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u32 bus_no, reg;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->set_cfg_type)
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if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
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if (bus->number != hose->first_busno)
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if (bus->number != hose->first_busno)
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cfg_type = 1;
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cfg_type = 1;
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bus_no = (bus->number == hose->first_busno) ?
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bus_no = (bus->number == hose->first_busno) ?
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hose->self_busno : bus->number;
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hose->self_busno : bus->number;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
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reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
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else
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reg = offset & 0xfc;
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PCI_CFG_OUT(hose->cfg_addr,
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | (bus_no << 16)
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(0x80000000 | (bus_no << 16)
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| (devfn << 8) | ((offset & 0xfc) | cfg_type)));
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| (devfn << 8) | reg | cfg_type));
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/*
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/*
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* Note: the caller has already checked that offset is
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* Note: the caller has already checked that offset is
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@ -65,9 +65,19 @@ struct pci_controller {
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/*
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/*
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* If set, indirect method will set the cfg_type bit as
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* If set, indirect method will set the cfg_type bit as
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* needed to generate type 1 configuration transactions.
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* needed to generate type 1 configuration transactions.
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* use only on ARCH=ppc
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*/
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*/
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int set_cfg_type;
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int set_cfg_type;
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/*
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* Used for variants of PCI indirect handling and possible quirks:
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* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
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* EXT_REG - provides access to PCI-e extended registers
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*/
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#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
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#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
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u32 indirect_type;
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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* ranges since the common pci_bus structure can't handle more
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* ranges since the common pci_bus structure can't handle more
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*/
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*/
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