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drm/panel: Add display timing for HannStar HSD070PWW1 

The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges
additionally to the typical values for pixel clock rate (64.3-82 MHz)
and blanking intervals (54-681 clock cycles horizontally, 3-23 lines
vertically).

This patch replaces this panel's display mode with the display timing
information to describe acceptable timings. Since the HSYNC and VSYNC
are unused, the distribution between front porches, back porches, and
sync pulse lengths was chosen at will.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Philipp Zabel 2014-12-11 18:32:46 +01:00 committed by Thierry Reding
parent a5d3e62514
commit ab07725abc
1 changed files with 13 additions and 13 deletions
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26
drivers/gpu/drm/panel/panel-simple.c
View File

@ -683,22 +683,22 @@ static const struct panel_desc giantplus_gpg482739qs5 = {
.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
};
static const struct drm_display_mode hannstar_hsd070pww1_mode = {
.clock = 71100,
.hdisplay = 1280,
.hsync_start = 1280 + 1,
.hsync_end = 1280 + 1 + 158,
.htotal = 1280 + 1 + 158 + 1,
.vdisplay = 800,
.vsync_start = 800 + 1,
.vsync_end = 800 + 1 + 21,
.vtotal = 800 + 1 + 21 + 1,
.vrefresh = 60,
static const struct display_timing hannstar_hsd070pww1_timing = {
.pixelclock = { 64300000, 71100000, 82000000 },
.hactive = { 1280, 1280, 1280 },
.hfront_porch = { 1, 1, 10 },
.hback_porch = { 1, 1, 10 },
.hsync_len = { 52, 158, 661 },
.vactive = { 800, 800, 800 },
.vfront_porch = { 1, 1, 10 },
.vback_porch = { 1, 1, 10 },
.vsync_len = { 1, 21, 203 },
.flags = DISPLAY_FLAGS_DE_HIGH,
};
static const struct panel_desc hannstar_hsd070pww1 = {
.modes = &hannstar_hsd070pww1_mode,
.num_modes = 1,
.timings = &hannstar_hsd070pww1_timing,
.num_timings = 1,
.bpc = 6,
.size = {
.width = 151,