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ARM: cache-v7: optimise test for Cortex A9 r0pX devices 

Eliminate one unnecessary instruction from this test by pre-shifting
the Cortex A9 ID - we can shift the actual ID in the teq instruction
thereby losing the pX bit of the ID at no cost.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2015-04-03 11:32:34 +01:00
parent d3cd451dfb
commit aaf4b5d92c
1 changed files with 3 additions and 4 deletions
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7
arch/arm/mm/cache-v7.S
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@ -97,10 +97,9 @@ ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position
#ifdef CONFIG_ARM_ERRATA_643719 #ifdef CONFIG_ARM_ERRATA_643719
ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register
ALT_UP( ret lr) @ LoUU is zero, so nothing to do ALT_UP( ret lr) @ LoUU is zero, so nothing to do
movw r1, #:lower16:0x410fc090 @ ID of ARM Cortex A9 r0p? movw r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p?
movt r1, #:upper16:0x410fc090 movt r1, #:upper16:(0x410fc090 >> 4)
bic r2, r2, #0x0000000f @ clear minor revision number teq r1, r2, lsr #4 @ test for errata affected core and if so...
teq r2, r1 @ test for errata affected core and if so...
moveq r3, #1 << 1 @ fix LoUIS value moveq r3, #1 << 1 @ fix LoUIS value
beq start_flush_levels @ start flushing cache levels beq start_flush_levels @ start flushing cache levels
#endif #endif