Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Ingo Molnar: "A handful of fixes: - Fix an MCE corner case bug/crash found via MCE injection testing - Fix 5-level paging boot crash - Fix MCE recovery cache invalidation bug - Fix regression on Xen guests caused by a recent PMD level mremap speedup optimization" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/mm: Make set_pmd_at() paravirt aware x86/mm/cpa: Fix set_mce_nospec() x86/boot/compressed/64: Do not corrupt EDX on EFER.LME=1 setting x86/MCE: Initialize mce.bank in the case of a fatal error in mce_no_way_out()
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commit
aadaa80611
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@ -602,10 +602,12 @@ ENTRY(trampoline_32bit_src)
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3:
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/* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */
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pushl %ecx
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pushl %edx
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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wrmsr
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popl %edx
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popl %ecx
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/* Enable PAE and LA57 (if required) paging modes */
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@ -1065,7 +1065,7 @@ static inline void native_set_pte_at(struct mm_struct *mm, unsigned long addr,
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static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
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pmd_t *pmdp, pmd_t pmd)
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{
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native_set_pmd(pmdp, pmd);
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set_pmd(pmdp, pmd);
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}
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static inline void set_pud_at(struct mm_struct *mm, unsigned long addr,
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@ -784,6 +784,7 @@ static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
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quirk_no_way_out(i, m, regs);
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if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
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m->bank = i;
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mce_read_aux(m, i);
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*msg = tmp;
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return 1;
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@ -230,6 +230,29 @@ static bool __cpa_pfn_in_highmap(unsigned long pfn)
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#endif
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/*
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* See set_mce_nospec().
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*
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* Machine check recovery code needs to change cache mode of poisoned pages to
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* UC to avoid speculative access logging another error. But passing the
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* address of the 1:1 mapping to set_memory_uc() is a fine way to encourage a
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* speculative access. So we cheat and flip the top bit of the address. This
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* works fine for the code that updates the page tables. But at the end of the
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* process we need to flush the TLB and cache and the non-canonical address
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* causes a #GP fault when used by the INVLPG and CLFLUSH instructions.
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*
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* But in the common case we already have a canonical address. This code
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* will fix the top bit if needed and is a no-op otherwise.
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*/
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static inline unsigned long fix_addr(unsigned long addr)
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{
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#ifdef CONFIG_X86_64
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return (long)(addr << 1) >> 1;
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#else
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return addr;
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#endif
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}
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static unsigned long __cpa_addr(struct cpa_data *cpa, unsigned long idx)
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{
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if (cpa->flags & CPA_PAGES_ARRAY) {
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@ -313,7 +336,7 @@ void __cpa_flush_tlb(void *data)
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unsigned int i;
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for (i = 0; i < cpa->numpages; i++)
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__flush_tlb_one_kernel(__cpa_addr(cpa, i));
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__flush_tlb_one_kernel(fix_addr(__cpa_addr(cpa, i)));
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}
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static void cpa_flush(struct cpa_data *data, int cache)
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@ -347,7 +370,7 @@ static void cpa_flush(struct cpa_data *data, int cache)
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* Only flush present addresses:
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*/
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if (pte && (pte_val(*pte) & _PAGE_PRESENT))
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clflush_cache_range_opt((void *)addr, PAGE_SIZE);
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clflush_cache_range_opt((void *)fix_addr(addr), PAGE_SIZE);
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}
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mb();
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}
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@ -1627,29 +1650,6 @@ out:
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return ret;
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}
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/*
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* Machine check recovery code needs to change cache mode of poisoned
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* pages to UC to avoid speculative access logging another error. But
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* passing the address of the 1:1 mapping to set_memory_uc() is a fine
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* way to encourage a speculative access. So we cheat and flip the top
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* bit of the address. This works fine for the code that updates the
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* page tables. But at the end of the process we need to flush the cache
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* and the non-canonical address causes a #GP fault when used by the
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* CLFLUSH instruction.
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*
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* But in the common case we already have a canonical address. This code
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* will fix the top bit if needed and is a no-op otherwise.
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*/
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static inline unsigned long make_addr_canonical_again(unsigned long addr)
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{
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#ifdef CONFIG_X86_64
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return (long)(addr << 1) >> 1;
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#else
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return addr;
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#endif
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}
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static int change_page_attr_set_clr(unsigned long *addr, int numpages,
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pgprot_t mask_set, pgprot_t mask_clr,
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int force_split, int in_flag,
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