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MIPS: bitops: Avoid redundant zero-comparison for non-LLSC 

The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already
return a zero or one, so there's no need to perform another comparison
against zero. Move these comparisons into the LLSC paths to avoid the
redundant work.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Paul Burton 2019-10-01 21:53:32 +00:00
parent d6103510e7
commit aad028cadb
No known key found for this signature in database
GPG Key ID: 3EA79FACB57500DD
1 changed files with 12 additions and 6 deletions
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18
arch/mips/include/asm/bitops.h
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@ -264,6 +264,8 @@ static inline int test_and_set_bit_lock(unsigned long nr,
: "=&r" (temp), "+m" (*m), "=&r" (res) : "=&r" (temp), "+m" (*m), "=&r" (res)
: "ir" (BIT(bit)) : "ir" (BIT(bit))
: __LLSC_CLOBBER); : __LLSC_CLOBBER);
res = res != 0;
} else { } else {
loongson_llsc_mb(); loongson_llsc_mb();
do { do {
@ -279,12 +281,12 @@ static inline int test_and_set_bit_lock(unsigned long nr,
: __LLSC_CLOBBER); : __LLSC_CLOBBER);
} while (unlikely(!res)); } while (unlikely(!res));
res = temp & BIT(bit); res = (temp & BIT(bit)) != 0;
} }
smp_llsc_mb(); smp_llsc_mb();
return res != 0; return res;
} }
/* /*
@ -335,6 +337,8 @@ static inline int test_and_clear_bit(unsigned long nr,
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "ir" (BIT(bit)) : "ir" (BIT(bit))
: __LLSC_CLOBBER); : __LLSC_CLOBBER);
res = res != 0;
} else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) { } else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) {
loongson_llsc_mb(); loongson_llsc_mb();
do { do {
@ -363,12 +367,12 @@ static inline int test_and_clear_bit(unsigned long nr,
: __LLSC_CLOBBER); : __LLSC_CLOBBER);
} while (unlikely(!res)); } while (unlikely(!res));
res = temp & BIT(bit); res = (temp & BIT(bit)) != 0;
} }
smp_llsc_mb(); smp_llsc_mb();
return res != 0; return res;
} }
/* /*
@ -403,6 +407,8 @@ static inline int test_and_change_bit(unsigned long nr,
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "ir" (BIT(bit)) : "ir" (BIT(bit))
: __LLSC_CLOBBER); : __LLSC_CLOBBER);
res = res != 0;
} else { } else {
loongson_llsc_mb(); loongson_llsc_mb();
do { do {
@ -418,12 +424,12 @@ static inline int test_and_change_bit(unsigned long nr,
: __LLSC_CLOBBER); : __LLSC_CLOBBER);
} while (unlikely(!res)); } while (unlikely(!res));
res = temp & BIT(bit); res = (temp & BIT(bit)) != 0;
} }
smp_llsc_mb(); smp_llsc_mb();
return res != 0; return res;
} }
#include <asm-generic/bitops/non-atomic.h> #include <asm-generic/bitops/non-atomic.h>