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MIPS: Malta: Move MSC01 interrupt base 

The GIC on Malta boards supports a total of 47 interrupts (40 shared
and 7 local) and is assigned a base of 24.  This overlaps with the
MSC01 interrupt assignments which have a base of 64, so move the MSC01
interrupt base back a bit to give the GIC some room.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Tested-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7815/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker 2014-09-18 14:47:17 -07:00 committed by Ralf Baechle
parent dfc94d1b21
commit aa827b748d
1 changed files with 4 additions and 4 deletions
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8
arch/mips/include/asm/mips-boards/maltaint.h
View File

@ -33,18 +33,18 @@
#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
/*
* Interrupts 64..127 are used for Soc-it Classic interrupts
* Interrupts 96..127 are used for Soc-it Classic interrupts
*/
#define MSC01C_INT_BASE 64
#define MSC01C_INT_BASE 96
/* SOC-it Classic interrupt offsets */
#define MSC01C_INT_TMR 0
#define MSC01C_INT_PCI 1
/*
* Interrupts 64..127 are used for Soc-it EIC interrupts
* Interrupts 96..127 are used for Soc-it EIC interrupts
*/
#define MSC01E_INT_BASE 64
#define MSC01E_INT_BASE 96
/* SOC-it EIC interrupt offsets */
#define MSC01E_INT_SW0 1