power: reset: ocelot: Add support 2 other MIPS based SoCs
This adds reset support for Luton and Jaguar2 in the ocelot-reset driver. They are both MIPS based belonging to the Vcore III family. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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@ -29,6 +29,8 @@ struct ocelot_reset_context {
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struct notifier_block restart_handler;
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};
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#define BIT_OFF_INVALID 32
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#define SOFT_CHIP_RST BIT(0)
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#define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
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@ -50,9 +52,11 @@ static int ocelot_restart_handle(struct notifier_block *this,
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ctx->props->vcore_protect, 0);
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/* Make the SI back to boot mode */
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regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
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IF_SI_OWNER_MASK << if_si_owner_bit,
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IF_SI_OWNER_SIBM << if_si_owner_bit);
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if (if_si_owner_bit != BIT_OFF_INVALID)
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regmap_update_bits(ctx->cpu_ctrl,
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ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
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IF_SI_OWNER_MASK << if_si_owner_bit,
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IF_SI_OWNER_SIBM << if_si_owner_bit);
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pr_emerg("Resetting SoC\n");
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@ -96,6 +100,20 @@ static int ocelot_reset_probe(struct platform_device *pdev)
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return err;
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}
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static const struct reset_props reset_props_jaguar2 = {
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.syscon = "mscc,ocelot-cpu-syscon",
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.protect_reg = 0x20,
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.vcore_protect = BIT(2),
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.if_si_owner_bit = 6,
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};
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static const struct reset_props reset_props_luton = {
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.syscon = "mscc,ocelot-cpu-syscon",
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.protect_reg = 0x20,
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.vcore_protect = BIT(2),
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.if_si_owner_bit = BIT_OFF_INVALID, /* n/a */
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};
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static const struct reset_props reset_props_ocelot = {
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.syscon = "mscc,ocelot-cpu-syscon",
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.protect_reg = 0x20,
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@ -112,6 +130,12 @@ static const struct reset_props reset_props_sparx5 = {
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static const struct of_device_id ocelot_reset_of_match[] = {
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{
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.compatible = "mscc,jaguar2-chip-reset",
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.data = &reset_props_jaguar2
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}, {
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.compatible = "mscc,luton-chip-reset",
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.data = &reset_props_luton
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}, {
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.compatible = "mscc,ocelot-chip-reset",
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.data = &reset_props_ocelot
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}, {
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